公开(公告)号：US12236104B2

公开(公告)日：2025-02-25

申请号：US17889117

申请日：2022-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Jeong Kim ,  Tae-Kyeong Ko ,  Nam Hyung Kim ,  Do-Han Kim ,  Deokho Seo ,  Ho-Young Lee ,  Insu Choi

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/07

Abstract: An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.

公开(公告)号：US12132501B2

公开(公告)日：2024-10-29

申请号：US17895227

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjae Shin ,  Sung-Joon Kim ,  Heedong Kim ,  Minsu Bae ,  Ilwoong Seo ,  Mijin Lee ,  Seung Ju Lee ,  Hyan Suk Lee ,  Insu Choi ,  Kideok Han

IPC: H03M13/19 ,  G06F11/10 ,  G11C5/04 ,  G11C8/08 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/52 ,  H03M13/00

CPC classification number: H03M13/19 ,  G06F11/10 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1048 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4096 ,  G11C29/52 ,  H03M13/611 ,  G11C5/04

Abstract: A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.

公开(公告)号：US11157342B2

公开(公告)日：2021-10-26

申请号：US16164103

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjae Shin ,  Tae-Kyeong Ko ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wooseop Kim ,  Chanik Park ,  Yongjun Yu ,  Insu Choi ,  Hui-Chung Byun ,  JongYoung Lee

IPC: G06F11/07

Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

公开(公告)号：US10521153B2

公开(公告)日：2019-12-31

申请号：US15492436

申请日：2017-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-Young Lim ,  Ki-Seok Oh ,  Sungyong Seo ,  Youngjin Cho ,  Insu Choi

IPC: G06F3/06 ,  G11C11/406 ,  G11C14/00

Abstract: A method for operating a storage device includes sending a request for a internal operation time for an internal operation to an external device, receiving an internal operation command corresponding to the request from the external device, and performing the internal operation during the internal operation time based on the internal operation command.

公开(公告)号：US11210208B2

公开(公告)日：2021-12-28

申请号：US16162821

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Jiseok Kang ,  Tae-Kyeong Ko ,  Sung-Joon Kim ,  Wooseop Kim ,  Chanik Park ,  Wonjae Shin ,  Yongjun Yu ,  Insu Choi

IPC: G06F12/02 ,  G11C11/56 ,  G06F3/06 ,  G06F13/16

Abstract: A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.

公开(公告)号：US10922170B2

公开(公告)日：2021-02-16

申请号：US16412468

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/406 ,  G11C11/00 ,  G11C29/52

Abstract: A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.

公开(公告)号：US20210042046A1

公开(公告)日：2021-02-11

申请号：US17082448

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun Yu ,  Insu Choi ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin

IPC: G06F3/06 ,  G06F12/0802

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

公开(公告)号：US10884655B2

公开(公告)日：2021-01-05

申请号：US16386645

申请日：2019-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Kim ,  Tae-Kyeong Ko ,  Dae-Jeong Kim ,  Do-Han Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Kwanghee Lee ,  Changmin Lee ,  Insu Choi

IPC: G06F3/06 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/02

Abstract: A storage module includes a dynamic random access memory (DRAM) device, a nonvolatile memory device, and a high-speed buffer memory. An method of operating the storage module includes copying target data stored in the nonvolatile memory device to the high-speed buffer memory in response to an external device entering a page fault mode, receiving a first refresh command from the external device, and, in response to the first refresh command, performing a first refresh operation associated with the DRAM device and moving the target data copied to the high-speed buffer memory to the DRAM device during a first refresh reference time.

公开(公告)号：US10740010B2

公开(公告)日：2020-08-11

申请号：US16205357

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Joon Kim ,  Dae-Jeong Kim ,  Wonjae Shin ,  Yongjun Yu ,  Insu Choi

IPC: G06F3/06

Abstract: A memory module includes a first type memory, a second type memory, a serial presence detect device and a controller. The serial presence detect device is configured to transfer capacity information of the second type memory to an external host device, during an initialization operation. The controller is configured to transfer a training command for the second type memory received from the external host device to the first type memory, during a training operation, which follows in time the initialization operation.

公开(公告)号：US12141478B2

公开(公告)日：2024-11-12

申请号：US17932734

申请日：2022-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deokho Seo ,  Taekyeong Ko ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Hoyoung Lee ,  Insu Choi

IPC: G06F3/06 ,  H03M13/00 ,  H03M13/11

Abstract: A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.