公开(公告)号：US09042503B2

公开(公告)日：2015-05-26

申请号：US13718403

申请日：2012-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Shin Shin

IPC: H04L7/00 ,  H04L7/04

CPC classification number: H04L7/0016 ,  H04L7/048

Abstract: In a data recovery circuit, a sampling circuit is configured to sample data using a plurality of sampling clock signals having different phases relative to one another and to output a plurality of sampled data. A recovery data generation circuit is configured to perform a logic operation on the plurality of sampled data and to generate a plurality of intermediate recovery data according to a result of the logic operation. A recovery circuit is configured to check the plurality of intermediate recovery data for existence of an error and to output intermediate recovery data that is error-free, among the plurality of intermediate recovery data, as recovery data.

Abstract translation: 在数据恢复电路中，采样电路被配置为使用具有相对于彼此具有不同相位的多个采样时钟信号对数据进行采样并输出多个采样数据。 恢复数据生成电路被配置为对多个采样数据执行逻辑运算，并根据逻辑运算的结果产生多个中间恢复数据。 恢复电路被配置为检查多个中间恢复数据以存在错误，并且在多个中间恢复数据中输出作为恢复数据的无错误的中间恢复数据。

公开(公告)号：US08949680B2

公开(公告)日：2015-02-03

申请号：US13755576

申请日：2013-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Su Chae ,  Jong Shin Shin

IPC: G01R31/28 ,  G06F11/00 ,  G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31715

Abstract: A data receiver device includes a logic unit configured to generate a test pattern signal, receive a test result signal in the test mode, and compare the test pattern signal with the test result signal to perform a test in the test mode. The data receiver further includes a system frequency control circuit configured to multiply a reference clock signal by a multiplication factor received from the logic unit and to output a test clock signal, an output terminal configured to serialize the test pattern signal based on the test clock signal and to output an output signal, and an input terminal configured to recover a data signal and a data clock signal from an input signal based on the output signal, to deserialize the data signal based on the data clock signal, and to output the test result signal to the logic unit.

Abstract translation: 一种数据接收装置包括：一个逻辑单元，被配置为产生测试模式信号，在测试模式下接收测试结果信号，并将测试模式信号与测试结果信号进行比较，以便在测试模式下进行测试。 数据接收机还包括系统频率控制电路，其被配置为将参考时钟信号乘以从逻辑单元接收的乘法因子并输出测试时钟信号，输出端子被配置为基于测试时钟信号串行化测试模式信号 并且输出输出信号，以及输入端子，被配置为基于输出信号从输入信号恢复数据信号和数据时钟信号，以基于数据时钟信号反序列化数据信号，并输出测试结果 信号到逻辑单元。

公开(公告)号：US10128822B2

公开(公告)日：2018-11-13

申请号：US15405893

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Han Bae ,  Jae Hyun Park ,  Jong Shin Shin ,  Jin Ho Han

IPC: H03B1/00 ,  H03K3/00 ,  H03K5/04

Abstract: An integrated circuit includes a differential signal driver that receives a first signal from a first input terminal, receives a second signal, which is a differential signal of the first signal, from a second input terminal, outputs a first output signal corresponding to the first signal to a first output terminal, and outputs a second output signal corresponding to the second signal to a second output terminal. The integrated circuit further includes a first capacitor unit connected to the first output terminal and controlling a slew rate of the first output signal based on a first capacitance, a second capacitor unit connected to the second output terminal and controlling a slew rate of the second output signal based on a second capacitance, and a phase selection unit that receives the first signal and provides the first signal to the second capacitor unit, and that receives the second signal and provides the second signal to the first capacitor unit, so as to control the slew rates of the first and second output signals.

公开(公告)号：US20130259177A1

公开(公告)日：2013-10-03

申请号：US13718403

申请日：2012-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Shin Shin

IPC: H04L7/00

CPC classification number: H04L7/0016 ,  H04L7/048

Abstract: In a data recovery circuit, a sampling circuit is configured to sample data using a plurality of sampling clock signals having different phases relative to one another and to output a plurality of sampled data. A recovery data generation circuit is configured to perform a logic operation on the plurality of sampled data and to generate a plurality of intermediate recovery data according to a result of the logic operation. A recovery circuit is configured to check the plurality of intermediate recovery data for existence of an error and to output intermediate recovery data that is error-free, among the plurality of intermediate recovery data, as recovery data.

Abstract translation: 在数据恢复电路中，采样电路被配置为使用具有相对于彼此具有不同相位的多个采样时钟信号对数据进行采样并输出多个采样数据。 恢复数据生成电路被配置为对多个采样数据执行逻辑运算，并根据逻辑运算的结果产生多个中间恢复数据。 恢复电路被配置为检查多个中间恢复数据以存在错误，并且在多个中间恢复数据中输出作为恢复数据的无错误的中间恢复数据。