公开(公告)号：US20180174958A1

公开(公告)日：2018-06-21

申请号：US15674878

申请日：2017-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se-Il OH ,  Jung-Ha OH ,  Hyuck-Joon KWON ,  Jong-Hyuk KIM ,  Jong-Moon YOON

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/485 ,  H01L23/58 ,  H01L23/482 ,  H01L23/14

CPC classification number: H01L23/5223 ,  H01L23/147 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/00 ,  H01L28/87

Abstract: A semiconductor device may include an insulating layer, a pad, a circuit, at least one first wiring, at least-one second wiring, at least one third wiring, and a pad contact. The pad may be disposed on the insulating layer. The circuit may be disposed in the insulating layer. The circuit may be positioned below the pad. The first wiring may be disposed between the pad and the circuit. The second wiring may be disposed between the pad and the first wiring. The third wiring may be disposed between the pad and the second wiring. The pad contact may be configured to directly connect the pad to the circuit.

公开(公告)号：US20160148808A1

公开(公告)日：2016-05-26

申请号：US14554107

申请日：2014-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hyuk KIM ,  Kang-III SEO ,  Hyun-Jae KANG ,  Deok-Han BAE

IPC: H01L21/033 ,  H01L21/308 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L29/66795 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.

Abstract translation: 提供一种制造半导体器件的方法。 在基板上形成多个目标图案。 多个目标图案沿着第一方向彼此平行地延伸。 形成在第一方向上延伸并且包括多个第一开口的第一掩模图案。 形成沿与第一方向交叉的第二方向延伸并且包括多个第二开口的第二掩模图案。 每个第二开口与每个第一开口重叠以形成重叠的开口区域。 使用第一掩模图案和第二掩模图案作为蚀刻掩模，通过重叠的开口区域蚀刻多个目标图案的区域。 多个目标图案的区域与重叠的开口区域重叠。

公开(公告)号：US20180294547A1

公开(公告)日：2018-10-11

申请号：US15766249

申请日：2016-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Chul PARK ,  Yeon-Woo KIM ,  Jong-Hyuk KIM ,  Seung-Gil JEON ,  Young-Ju KIM ,  Chae-Man LIM

IPC: H01Q1/24 ,  H04W88/06 ,  H04B1/00 ,  H01Q21/00

Abstract: An electronic apparatus, according to various embodiments of the present invention, comprises: a first antenna of a first bandwidth; a second antenna of a second bandwidth which partially overlaps with the first bandwidth; a third antenna of the first bandwidth; a fourth antenna of the second bandwidth; a transmission/reception path corresponding to each of a plurality of bandwidths; a reception path corresponding to each of the plurality of bandwidths; and a path formation unit which forms a path such that any one of the first antenna and the third antenna is connected to the transmission/reception path, the other of the first antenna and the third antenna is connected to the reception path, and any one of the second antenna and the fourth antenna is connected to the transmission/reception path, and the other of the second antenna and the fourth antenna is connected to the reception path.

公开(公告)号：US20200144176A1

公开(公告)日：2020-05-07

申请号：US16582706

申请日：2019-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se-Il OH ,  Jung-Ha OH ,  Hyuck-Joon KWON ,  Jong-Hyuk KIM ,  Jong-Moon YOON

IPC: H01L23/522 ,  H01L23/14 ,  H01L23/482 ,  H01L23/58 ,  H01L23/485 ,  H01L49/02 ,  H01L23/00 ,  H01L23/532

Abstract: A semiconductor device may include an insulating layer, a pad, a circuit, at least one first wiring, at least one second wiring, at least one third wiring, and a pad contact. The pad may be disposed on the insulating layer. The circuit may be disposed in the insulating layer. The circuit may be positioned below the pad. The first wiring may be disposed between the pad and the circuit. The second wiring may be disposed between the pad and the first wiring. The third wiring may be disposed between the pad and the second wiring. The pad contact may be configured to directly connect the pad to the circuit.