公开(公告)号：US10249627B2

公开(公告)日：2019-04-02

申请号：US15621315

申请日：2017-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Hoon Han ,  Dong Wan Kim ,  Ji Hun Kim ,  Jae Joon Song ,  Hiroshi Takeda

IPC: H01L27/108 ,  H01L49/02

Abstract: A semiconductor device is provided. The semiconductor device includes an upper interlayer insulating layer disposed on a substrate. A first electrode spaced apart from the upper interlayer insulating layer is disposed on the substrate. A contact structure penetrating the upper interlayer insulating layer is disposed on the substrate. An upper support layer having a first portion covering an upper surface of the upper interlayer insulating layer, to surround an upper side surface of the contact structure, and a second portion extending in a horizontal direction from the first portion and surrounding an upper side surface of the first electrode, is disposed. A dielectric conformally covering the first electrode and a second electrode on the dielectric are disposed.

公开(公告)号：US12185528B2

公开(公告)日：2024-12-31

申请号：US18403817

申请日：2024-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Oh Kim ,  Gyu Hyun Kil ,  Jung Hoon Han ,  Doo San Back

IPC: H10B12/00

Abstract: A semiconductor memory device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a profile of the boundary element isolation recess and a first gate structure on the core region and at least a part of the boundary element isolation layer, wherein the first gate structure includes a first high dielectric layer, and a first gate insulating pattern below the first high dielectric layer, with a top surface of the substrate being a base reference level, the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high dielectric layer, and a first_2 gate insulating pattern disposed a top surface of the core region and a bottom surface of the first high dielectric layer.

公开(公告)号：US20220173112A1

公开(公告)日：2022-06-02

申请号：US17406418

申请日：2021-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Oh Kim ,  Gyu Hyun Kil ,  Jung Hoon Han ,  Doo San Back

IPC: H01L27/108

Abstract: A semiconductor memory device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a profile of the boundary element isolation recess and a first gate structure on the core region and at least a part of the boundary element isolation layer, wherein the first gate structure includes a first high dielectric layer, and a first gate insulating pattern below the first high dielectric layer, with a top surface of the substrate being a base reference level, the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high dielectric layer, and a first_2 gate insulating pattern disposed a top surface of the core region and a bottom surface of the first high dielectric layer.

公开(公告)号：US11895833B2

公开(公告)日：2024-02-06

申请号：US17406418

申请日：2021-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Oh Kim ,  Gyu Hyun Kil ,  Jung Hoon Han ,  Doo San Back

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/315 ,  H10B12/34

Abstract: A semiconductor memory device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a profile of the boundary element isolation recess and a first gate structure on the core region and at least a part of the boundary element isolation layer, wherein the first gate structure includes a first high dielectric layer, and a first gate insulating pattern below the first high dielectric layer, with a top surface of the substrate being a base reference level, the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high dielectric layer, and a first_2 gate insulating pattern disposed a top surface of the core region and a bottom surface of the first high dielectric layer.

公开(公告)号：US20240147709A1

公开(公告)日：2024-05-02

申请号：US18403817

申请日：2024-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Oh Kim ,  Gyu Hyun Kil ,  Jung Hoon Han ,  Doo San Back

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/315 ,  H10B12/34

Abstract: A semiconductor memory device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a profile of the boundary element isolation recess and a first gate structure on the core region and at least a part of the boundary element isolation layer, wherein the first gate structure includes a first high dielectric layer, and a first gate insulating pattern below the first high dielectric layer, with a top surface of the substrate being a base reference level, the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high dielectric layer, and a first_2 gate insulating pattern disposed a top surface of the core region and a bottom surface of the first high dielectric layer.

公开(公告)号：US10134740B2

公开(公告)日：2018-11-20

申请号：US15644877

申请日：2017-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Wan Kim ,  Ji Hun Kim ,  Jae Joon Song ,  Hiroshi Takeda ,  Jung Hoon Han

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L23/528 ,  H01L21/28 ,  H01L21/02

Abstract: A semiconductor device including a substrate; a trench formed within the substrate; a gate insulating film formed conformally along a portion of a surface of the trench; a gate electrode formed on the gate insulating film and filling a portion of the trench; a capping film formed on the gate electrode and filling the trench; and an air gap formed between the capping film and the gate insulating film.