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公开(公告)号：US20240047390A1
公开(公告)日：2024-02-08
申请号：US18377530
申请日：2023-10-06
发明人： Minjung CHOI , Sooho SHIN , Yeonjin LEE , Junghoon HAN
CPC分类号： H01L24/05 , H01L21/561 , H01L24/13 , H01L24/96 , H01L24/73 , H01L2224/81801 , H01L2924/1304 , H01L2924/18162 , H01L2224/0401 , H01L2224/13099 , H01L2224/12105
摘要： A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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公开(公告)号：US20230354590A1
公开(公告)日：2023-11-02
申请号：US18220327
申请日：2023-07-11
发明人： Dongoh KIM , Gyuhyun KIL , Junghoon HAN , Doosan BACK
IPC分类号： H10B12/00 , H01L27/092
CPC分类号： H10B12/50 , H01L27/092 , H10B12/315
摘要： A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.
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公开(公告)号：US20230178634A1
公开(公告)日：2023-06-08
申请号：US18072784
申请日：2022-12-01
发明人： Jeonil LEE , Gyuhyun KIL , Doosan BACK , Chansic YOON , Junghoon HAN
IPC分类号： H01L29/66 , H10B12/00 , H01L29/78 , H01L29/423
CPC分类号： H01L29/6656 , H01L27/10897 , H01L27/10894 , H01L29/7833 , H01L29/6659 , H01L29/42364 , H01L27/10814 , H01L27/10885 , H01L27/10823
摘要： A semiconductor device includes a substrate, a gate dielectric layer on the substrate, the gate dielectric layer including a recess at a side surface thereof, a gate electrode structure on the gate dielectric layer, a gate capping layer on the gate electrode structure, and a spacer structure on the substrate and covering side surfaces of the gate dielectric layer, the gate electrode structure, and the gate capping layer, the spacer structure including a first spacer, a second spacer on the first spacer and covering the recess, and a third spacer on the second spacer, the second spacer and the third spacer including silicon nitride.
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公开(公告)号：US20220189969A1
公开(公告)日：2022-06-16
申请号：US17386008
申请日：2021-07-27
发明人： Dongoh KIM , Gyuhyun KIL , Junghoon HAN , Doosan BACK
IPC分类号： H01L27/108 , H01L27/092
摘要： A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.
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公开(公告)号：US20220189967A1
公开(公告)日：2022-06-16
申请号：US17371558
申请日：2021-07-09
发明人： Dongoh KIM , Gyuhyun KIL , Junghoon HAN , Doosan BACK
IPC分类号： H01L27/108
摘要： A semiconductor memory device may have a substrate including an active region in a memory cell region and a logic active region in a peripheral region, an element isolation structure between the active region and the logic active region, an insulating layer pattern covering the active region, and a support insulating layer. The insulating layer pattern may include an extension portion that extends along the element isolation structure, may be spaced apart from the element isolation structure, and may overhang over the element isolation structure. The support insulating layer may fill a recess space defined between the extension portion and the element isolation structure.
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公开(公告)号：US20210280541A1
公开(公告)日：2021-09-09
申请号：US17328365
申请日：2021-05-24
发明人： Minjung CHOI , Sooho SHIN , Yeonjin LEE , Junghoon HAN
摘要： A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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公开(公告)号：US20240363552A1
公开(公告)日：2024-10-31
申请号：US18768684
申请日：2024-07-10
发明人： Chulsoon CHANG , Sangki KIM , Ilgeun JUNG , Junghoon HAN
IPC分类号： H01L23/00 , H01L21/768
CPC分类号： H01L23/562 , H01L21/76877
摘要： A semiconductor device may include a semiconductor substrate, a crack-blocking layer and a crack-blocking portion. The semiconductor substrate may include a plurality of chip regions and a scribe lane region configured to surround each of the plurality of the chip regions. A trench may be defined by one or more inner surfaces of the semiconductor device to be formed in the scribe lane region. The crack-blocking layer may be on an inner surface of the trench. The crack-blocking layer may be configured to block a spreading of a crack, which is generated in the scribe lane region during a cutting of the semiconductor substrate along the scribe lane region, from spreading into any of the chip regions. The crack-blocking portion may at least partially fill the trench and may be configured to block the spreading of the crack from the scribe lane region into any of the chip regions.
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公开(公告)号：US20240274664A1
公开(公告)日：2024-08-15
申请号：US18409269
申请日：2024-01-10
发明人： Jungmin JU , Chansic YOON , Gyuhyun KIL , Junghoon HAN , Weonhong KIM
CPC分类号： H01L29/0847 , H10B12/50
摘要： An integrated circuit device includes a gate stack on a substrate, a spacer on first and second sidewalls of the gate stack, a source/drain area in an upper portion of the substrate on first and second sides of the gate stack, a cover semiconductor layer on the source/drain area, an interlayer insulating film on the cover semiconductor layer and surrounding sidewalls of the gate stack, and a contact in a contact hole that penetrates the interlayer insulating film and the cover semiconductor layer, the contact having a bottom portion contacting the cover semiconductor layer and the source/drain area.
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公开(公告)号：US20210375759A1
公开(公告)日：2021-12-02
申请号：US17398043
申请日：2021-08-10
发明人： Juik LEE , Joongwon SHIN , Jihoon CHANG , Junghoon HAN , Junwoo LEE
IPC分类号： H01L23/528 , H01L23/532 , H01L25/065 , H01L25/18 , H01L23/522 , H01L27/108 , H01L23/00 , H01L23/48
摘要： A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.
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公开(公告)号：US20210104462A1
公开(公告)日：2021-04-08
申请号：US16885438
申请日：2020-05-28
发明人： Juik LEE , Joongwon SHIN , Jihoon CHANG , Junghoon HAN , Junwoo LEE
IPC分类号： H01L23/528 , H01L23/48 , H01L23/532 , H01L25/065 , H01L25/18 , H01L23/522 , H01L27/108 , H01L23/00
摘要： A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.
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