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公开(公告)号：US20240047390A1
公开(公告)日：2024-02-08
申请号：US18377530
申请日：2023-10-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjung CHOI , Sooho SHIN , Yeonjin LEE , Junghoon HAN
CPC classification number: H01L24/05 , H01L21/561 , H01L24/13 , H01L24/96 , H01L24/73 , H01L2224/81801 , H01L2924/1304 , H01L2924/18162 , H01L2224/0401 , H01L2224/13099 , H01L2224/12105
Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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公开(公告)号：US20210280541A1
公开(公告)日：2021-09-09
申请号：US17328365
申请日：2021-05-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjung CHOI , Sooho SHIN , Yeonjin LEE , Junghoon HAN
Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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公开(公告)号：US20230076238A1
公开(公告)日：2023-03-09
申请号：US17882748
申请日：2022-08-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhyung KIM , Jong-Min LEE , Minjung CHOI , Jimin CHOI
IPC: H01L23/528 , H01L23/00 , H01L21/822 , H01L25/065 , H01L21/66
Abstract: Semiconductor chips, semiconductor packages, and semiconductor chip fabrication methods may be provided. The semiconductor chip includes a substrate including a device region and an edge region, a device layer and a wiring layer sequentially stacked on the substrate, a sub-pad on the device region and a residual test pattern on the edge region wherein a sidewall of the residual test pattern is aligned with a sidewall of the substrate, and an upper dielectric stack covering the sub-pad and the residual test pattern. The upper dielectric stack may expose a portion of a top surface of the residual test pattern. A sidewall of the upper dielectric stack may have a stepped region.
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公开(公告)号：US20210305115A1
公开(公告)日：2021-09-30
申请号：US17206295
申请日：2021-03-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minjung CHOI , Jung-Hoon HAN , Jiho KIM , Young-Yong BYUN , Yeonjin LEE , Jihoon CHANG
IPC: H01L23/31 , H01L23/528
Abstract: A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.
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公开(公告)号：US20220326301A1
公开(公告)日：2022-10-13
申请号：US17540745
申请日：2021-12-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jihoon CHANG , Yeonjin LEE , Minjung CHOI , Jimin CHOI
IPC: G01R31/28 , H01L23/522 , H01L23/528 , H01L23/00
Abstract: A detection pad structure in a semiconductor device may include a lower wiring on a substrate, an upper wiring on the lower wiring, and a first pad pattern on the upper wiring. The upper wiring may be connected to the lower wiring and include metal patterns and via contacts on the metal patterns that are stacked in a plurality of layers. The first pad pattern may be connected to the upper wiring. A semiconductor device may include an actual upper wiring including actual metal patterns and actual via contacts stacked in a plurality of layers. At least one of the metal patterns of each layer in the upper wiring may have a minimum line width and a minimum space of the metal patterns of each layer in the actual upper wiring. Metal patterns and via contacts of each layer in the upper wiring may be regularly and repeatedly arranged.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20210175133A1
公开(公告)日：2021-06-10
申请号：US16898943
申请日：2020-06-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjung CHOI , Junyong NOH , Yeonjin LEE , Junghoon HAN
Abstract: A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.
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公开(公告)号：US20230154876A1
公开(公告)日：2023-05-18
申请号：US18093880
申请日：2023-01-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjung CHOI , Sooho SHIN , Yeonjin LEE , Junghoon HAN
CPC classification number: H01L24/05 , H01L21/561 , H01L24/13 , H01L24/96 , H01L24/73 , H01L2224/81801 , H01L2924/1304 , H01L2924/18162 , H01L2224/0401 , H01L2224/13099 , H01L2224/12105
Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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公开(公告)号：US20210043591A1
公开(公告)日：2021-02-11
申请号：US16795658
申请日：2020-02-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjung CHOI , Sooho SHIN , Yeonjin LEE , Junghoon HAN
Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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公开(公告)号：US20230077803A1
公开(公告)日：2023-03-16
申请号：US17751740
申请日：2022-05-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jimin CHOI , Jongmin LEE , Yeonjin LEE , Jeonil LEE , Juik LEE , Minjung CHOI
IPC: H01L23/48 , H01L23/00 , H01L25/065
Abstract: A semiconductor device includes a substrate, an etch stop layer on the substrate, a through-hole electrode extending through the substrate and the etch stop layer in a vertical direction substantially perpendicular to an upper surface of the substrate, and a conductive pad. The etch stop layer includes a first surface adjacent to the substrate and a second surface opposite the first surface. The through-hole electrode includes a protrusion portion that protrudes from the second surface of the etch stop layer. The conductive pad covers the protrusion portion of the through-hole electrode. The protrusion portion of the through-hole electrode is not flat.
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10.发明申请公开(公告)号：US20220223485A1
公开(公告)日：2022-07-14
申请号：US17706401
申请日：2022-03-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjung CHOI , Junyong NOH , Yeonjin LEE , Junghoon HAN
Abstract: A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.
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