公开(公告)号：US20220037307A1

公开(公告)日：2022-02-03

申请号：US17188077

申请日：2021-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungpil LEE

IPC: H01L27/02 ,  H01L23/48 ,  H01L23/522

Abstract: A semiconductor device includes a first integrated circuit and a second integrated circuit disposed on a semiconductor substrate and spaced apart from each other. A wiring structure is disposed on the semiconductor substrate and electrically connects the first integrated circuit and the second integrated circuit. A first TSV area and a second TSV area are disposed between the first integrated circuit and the second integrated circuit The first and second TSV areas include a plurality of first and second TSV structures penetrating through the semiconductor substrate, respectively. The wiring structure passes between the first TSV area and the second TSV area.

公开(公告)号：US20230121072A1

公开(公告)日：2023-04-20

申请号：US17879089

申请日：2022-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungpil LEE

IPC: G06F1/20 ,  H01L25/065 ,  H01L23/48 ,  G06F1/324 ,  G06F1/3237 ,  G06F1/3206 ,  G06F1/3287 ,  H01L23/34

Abstract: Disclosed are semiconductor packages and thermal management methods thereof. The semiconductor package includes an upper semiconductor chip; and a lower semiconductor chip connected via a plurality of through electrodes to the upper semiconductor chip. The lower semiconductor chip may include at least one temperature sensor configured to sense a temperature of the upper semiconductor chip, a power control unit connected to the at least one temperature sensor, a power switching element connected to at least a first one of the plurality of through electrodes, and a clock control element connected to at least a second one of the plurality of through electrodes.

公开(公告)号：US20220367553A1

公开(公告)日：2022-11-17

申请号：US17745010

申请日：2022-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungkyu KIM ,  Dong-Hun LEE ,  Woonbae KIM ,  Daeho LEE ,  Jungpil LEE

IPC: H01L27/146

Abstract: A semiconductor package including a substrate including a through hole, an image sensor structure on the substrate, and a first transparent substrate on the substrate and spaced apart from the image sensor structure may be provided. The image sensor structure includes a logic chip on the substrate, a first sensing chip on an active surface of the logic chip, and a second sensing chip on an inactive surface of the logic chip and connected to the active surface of the logic chip through a first via that vertically penetrates the logic chip. On a bottom surface of the logic chip, at least a portion of one of the first sensing chip and the second sensing chip is in the through hole.