LOW DROPOUT REGULATORS
    1.
    发明申请

    公开(公告)号:US20250060771A1

    公开(公告)日:2025-02-20

    申请号:US18806082

    申请日:2024-08-15

    Abstract: Provided are a low dropout (LDO) regulator controlling operation biasing of a transistor connected to an output node to have a wide bandwidth and provide a stable voltage at a fast speed, and a memory device including the LDO regulator. The LDO regulator includes a first low voltage transistor in which a first terminal thereof is connected to an output node configured to provide an output voltage to a load and a second terminal thereof is connected to a first node, an operational amplifier configured to compare a reference voltage with the output voltage and output the comparison result to a gate terminal of a first low voltage transistor, and an operation biasing control circuit connected to the output node and the first node, and including at least one high voltage transistor.

    LOW DROPOUT REGULATOR AND MEMORY DEVICE INCLUDING THE SAME

    公开(公告)号:US20250060769A1

    公开(公告)日:2025-02-20

    申请号:US18760350

    申请日:2024-07-01

    Abstract: An example low dropout (LDO) regulator includes a voltage regulating circuit and an adaptive biasing circuit. The voltage regulating circuit is configured to regulate an output voltage of an output node connected with a load by using the output voltage as first feedback. The adaptive biasing circuit is configured to generate a biasing signal that supports regulation of the output voltage by using a sensing signal in an internal node of the voltage regulating circuit as second feedback, and to provide the biasing signal to the voltage regulating circuit.

    Low dropout regulator and memory device including the same

    公开(公告)号:US11940830B2

    公开(公告)日:2024-03-26

    申请号:US17709853

    申请日:2022-03-31

    CPC classification number: G05F1/575 G11C11/4074 G11C11/4076 G11C11/4093

    Abstract: Disclosed is a low dropout regulator which includes a first resistor, a first transistor including a gate terminal connected with a first end of the first resistor, a source terminal connected with a power supply voltage terminal, and a drain terminal connected with a first node, an operational amplifier including input terminals respectively connected with a reference voltage and the first node and an output terminal, a second transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the first node, and a drain terminal connected with a second node, a third transistor including a gate terminal connected with a second end of the first resistor, a source terminal connected with the power supply voltage terminal, and a drain terminal connected with a third node, and a current source connected between the second node and a ground voltage terminal.

    Voltage regulator and semiconductor memory device having the same

    公开(公告)号:US11797038B2

    公开(公告)日:2023-10-24

    申请号:US17577201

    申请日:2022-01-17

    CPC classification number: G05F1/575 G11C5/147 G11C8/10 G11C8/18

    Abstract: A voltage regulator and a semiconductor memory device having the same are disclosed. The voltage regulator includes an amplifier configured to amplify a difference between a reference voltage and a feedback voltage to generate an amplifier output voltage, a voltage feedback unit connected between an output supply voltage generation node and a ground voltage and configured to generate the feedback voltage, a first transfer gate unit connected between an input supply voltage and the voltage generation node and driven in response to the amplifier output voltage to provide first current, a current load replica unit connected between the voltage generation node and the ground voltage and configured to consume the first current, and a transfer unit connected between the input supply voltage and the voltage generation node and driven in response to the amplifier output voltage when the current load unit performs an operation, to provide second current.

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