公开(公告)号：US11797038B2

公开(公告)日：2023-10-24

申请号：US17577201

申请日：2022-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woochul Jung ,  Myoungbo Kwak ,  Jaewoo Park ,  Eunseok Shin ,  Junhan Choi

IPC: G11C8/10 ,  G05F1/575 ,  G11C8/18 ,  G11C5/14

CPC classification number: G05F1/575 ,  G11C5/147 ,  G11C8/10 ,  G11C8/18

Abstract: A voltage regulator and a semiconductor memory device having the same are disclosed. The voltage regulator includes an amplifier configured to amplify a difference between a reference voltage and a feedback voltage to generate an amplifier output voltage, a voltage feedback unit connected between an output supply voltage generation node and a ground voltage and configured to generate the feedback voltage, a first transfer gate unit connected between an input supply voltage and the voltage generation node and driven in response to the amplifier output voltage to provide first current, a current load replica unit connected between the voltage generation node and the ground voltage and configured to consume the first current, and a transfer unit connected between the input supply voltage and the voltage generation node and driven in response to the amplifier output voltage when the current load unit performs an operation, to provide second current.

公开(公告)号：US11201626B1

公开(公告)日：2021-12-14

申请号：US17240570

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woochul Jung ,  Yongsun Lee

IPC: H03L7/197 ,  H03L7/089 ,  H03L7/093

Abstract: A phase locked loop device may include: a frequency modulating circuit configured to output a reference signal obtained by multiplying a frequency of an input signal by a predetermined ratio based on the input signal; a sigma-delta modulator configured to output division ratio information on one of a plurality of division rates at a number of times proportional to a frequency of the reference signal; and a phase locked loop (PLL) circuit configured to determine whether to activate based on a command signal, and, when activated, perform a phase-locking operation based on a fractional division based on the reference signal and the division ratio information.

公开(公告)号：US12019578B2

公开(公告)日：2024-06-25

申请号：US17899883

申请日：2022-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok Shin ,  Woochul Jung ,  Jungho Ko ,  Myoungbo Kwak ,  Jaewoo Park ,  Sunjae Lim ,  Junghwan Choi

IPC: G06F13/42 ,  G06F13/38 ,  H03K17/687 ,  H03M9/00

CPC classification number: G06F13/4204 ,  G06F13/4282 ,  H03M9/00 ,  G06F2213/0002 ,  G06F2213/0004 ,  H03K17/6871

Abstract: A parallel-to-serial interface circuit includes an equalizer to delay odd data by a half period and sequentially generate odd pre data, odd main data, and odd post data, and delay even data by a half period and sequentially generate even pre data, even main data, and even post data, a final parallel-to-serial converter to sequentially and alternately select the even pre data and the odd pre data to generate pre data, sequentially and alternately select inverted odd main data and inverted even main data to generate inverted main data, and sequentially and alternately select the even post data and the odd post data to generate post data, and a driver to drive the pre data to generate a pre data level, drive the inverted main data to generate an inverted main data level, and drive the post data to generate a post data level.