公开(公告)号：US20240203946A1

公开(公告)日：2024-06-20

申请号：US18537997

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyeong HEO ,  Unbyoung KANG ,  Sera LEE ,  Jihoon JUNG

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L29/06

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L23/481 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06565 ,  H01L2225/06568

Abstract: A semiconductor chip includes a semiconductor substrate having an active surface and an inactive surface opposite the active surface. A semiconductor device layer is disposed on the active surface. A modified region is positioned on an entirety of a lateral side surface of the semiconductor substrate.

公开(公告)号：US20250167031A1

公开(公告)日：2025-05-22

申请号：US18890154

申请日：2024-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hosin SONG ,  Yeongkwon KO ,  Jiyoung PARK ,  Junyeong HEO

IPC: H01L21/683 ,  H01L21/304 ,  H01L21/66 ,  H01L21/68

Abstract: A carrier substrate according to some example embodiments is a carrier substrate having a circular disk shape, and includes a first surface, a second surface opposite surface to first surface, and an inclined surface that extends along the edge of the first surface, has an inclination angle from the first surface, and is configured to reflect incident light from the second surface.

公开(公告)号：US20210343613A1

公开(公告)日：2021-11-04

申请号：US17117588

申请日：2020-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Seunghun SHIN ,  Junyeong HEO

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

公开(公告)号：US20240379478A1

公开(公告)日：2024-11-14

申请号：US18780720

申请日：2024-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Seunghun SHIN ,  Junyeong HEO

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

公开(公告)号：US20230034015A1

公开(公告)日：2023-02-02

申请号：US17938344

申请日：2022-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyeong HEO ,  Unbyoung KANG ,  Donghoon WON

IPC: H01L23/528 ,  H01L23/48 ,  H01L21/78 ,  H01L21/3065

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, and a side surface between the first and second surfaces, and including a device region on the first surface a wiring structure on the surface of the semiconductor substrate, and having a dielectric layer and a metal wiring in the dielectric layer and electrically connected to the device region, and an insulating material layer on a side surface of the wiring structure and having a side surface connected to the side surface of the semiconductor substrate. The side surface of the insulating material layer has a first wave-shaped pattern in which concave-convex portions are repeated in a direction of the wiring structure that is perpendicular to the semiconductor substrate, and the side surface of the semiconductor substrate has a second wave-shaped pattern in which concave-convex portions are repeated in the direction.

公开(公告)号：US20220399311A1

公开(公告)日：2022-12-15

申请号：US17667989

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyeong HEO ,  Yeongkwon KO ,  Unbyoung KANG ,  Teakhoon LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/78

Abstract: A semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, and an insulating adhesive layer between the first semiconductor chip, and each of the plurality of second semiconductor chips, each of the plurality second conductor chips, and the insulating adhesive layer including an adhesive fillet protruding from between at least the first semiconductor chip and each of the plurality of second semiconductor chips, wherein a grooving recess is defined by the first semiconductor chip, the plurality of second semiconductor chips, and the insulating adhesive layer, the grooving recess including a first recess and a second recess adjacent to the first recess, an uppermost surface of the adhesive fillet and the first semiconductor chip defines the first recess, and an uppermost surface of the first semiconductor chip to a surface inside the first semiconductor chip defines the second recess.

公开(公告)号：US20210125925A1

公开(公告)日：2021-04-29

申请号：US16886444

申请日：2020-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyeong HEO ,  Unbyoung KANG ,  Donghoon WON

IPC: H01L23/528 ,  H01L21/3065 ,  H01L21/78 ,  H01L23/48

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, and a side surface between the first and second surfaces, and including a device region on the first surface a wiring structure on the surface of the semiconductor substrate, and having a dielectric layer and a metal wiring in the dielectric layer and electrically connected to the device region, and an insulating material layer on a side surface of the wiring structure and having a side surface connected to the side surface of the semiconductor substrate. The side surface of the insulating material layer has a first wave-shaped pattern in which concave-convex portions are repeated in a direction of the wiring structure that is perpendicular to the semiconductor substrate, and the side surface of the semiconductor substrate has a second wave-shaped pattern in which concave-convex portions are repeated in the direction.