公开(公告)号：US20220013474A1

公开(公告)日：2022-01-13

申请号：US17083932

申请日：2020-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung YOO ,  Yeongkwon KO ,  Jayeon LEE ,  Jaeeun LEE ,  Teakhoon LEE

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package comprises a substrate; an interposer on the substrate; a first underfill between the substrate and the interposer; at least one logic chip and at least one memory stack on the interposer; and a molding material on the interposer while surrounding a side surface of the at least one logic chip and a side surface of the at least one memory stack. The molding material includes areas having different heights. The first underfill covers a portion of the molding material.

公开(公告)号：US20220285312A1

公开(公告)日：2022-09-08

申请号：US17804110

申请日：2022-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan HWANG ,  Unbyoung KANG ,  Sangsick PARK ,  Jihwan SUH ,  Soyoun LEE ,  Teakhoon LEE

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.

公开(公告)号：US20230197681A1

公开(公告)日：2023-06-22

申请号：US18110446

申请日：2023-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo PARK ,  Unbyoung KANG ,  Jongho LEE ,  Teakhoon LEE

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3675 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/562 ,  H01L23/3135 ,  H01L2225/06589 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view.

公开(公告)号：US20220013496A1

公开(公告)日：2022-01-13

申请号：US17168238

申请日：2021-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo PARK ,  Unbyoung KANG ,  Jongho LEE ,  Teakhoon LEE

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00

Abstract: A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view.

公开(公告)号：US20210375823A1

公开(公告)日：2021-12-02

申请号：US17142133

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan HWANG ,  Unbyoung KANG ,  Sangsick PARK ,  Jihwan SUH ,  Soyoun LEE ,  Teakhoon LEE

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.

公开(公告)号：US20230121888A1

公开(公告)日：2023-04-20

申请号：US17884695

申请日：2022-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsoo KIM ,  Jiho KIM ,  Unbyoung KANG ,  Sangsick PARK ,  Teakhoon LEE

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip including upper signal pads and upper dummy pads. A second semiconductor chip is on the first semiconductor chip, and includes lower signal pads and lower dummy pads. First conductive bumps are between the upper signal pads and the lower signal pads. Second conductive bumps are between the upper dummy pads and the lower dummy pads. The upper dummy pads include merged pads covering a plurality of adjacent lower dummy pads. A plurality of metal plating layers are disposed on each of the merged pads in areas respectively corresponding to the plurality of adjacent lower dummy pads. The second conductive bumps include a plurality of conductive bumps respectively disposed between the plurality of first metal plating layers and the plurality of adjacent lower dummy pads.

公开(公告)号：US20220399311A1

公开(公告)日：2022-12-15

申请号：US17667989

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyeong HEO ,  Yeongkwon KO ,  Unbyoung KANG ,  Teakhoon LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/78

Abstract: A semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, and an insulating adhesive layer between the first semiconductor chip, and each of the plurality of second semiconductor chips, each of the plurality second conductor chips, and the insulating adhesive layer including an adhesive fillet protruding from between at least the first semiconductor chip and each of the plurality of second semiconductor chips, wherein a grooving recess is defined by the first semiconductor chip, the plurality of second semiconductor chips, and the insulating adhesive layer, the grooving recess including a first recess and a second recess adjacent to the first recess, an uppermost surface of the adhesive fillet and the first semiconductor chip defines the first recess, and an uppermost surface of the first semiconductor chip to a surface inside the first semiconductor chip defines the second recess.

公开(公告)号：US20210320000A1

公开(公告)日：2021-10-14

申请号：US17078278

申请日：2020-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungseok AHN ,  Unbyoung KANG ,  Chungsun LEE ,  Teakhoon LEE

IPC: H01L21/02 ,  B24B21/00 ,  B26D7/18 ,  B28D5/02 ,  H01L21/304

Abstract: The wafer trimming device includes a chuck table configured to hold a target wafer via suction, thereby fixing the target wafer, a notch trimmer configured to trim a notch of the target wafer, and an edge trimmer configured to trim an edge of the target wafer. The notch trimmer includes a notch trimming blade configured to rotate about a rotation axis perpendicular to a circumferential surface of the target wafer. The edge trimmer includes an edge trimming blade configured to rotate about a rotation axis parallel to the circumferential surface of the target wafer.