公开(公告)号：US20210343613A1

公开(公告)日：2021-11-04

申请号：US17117588

申请日：2020-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Seunghun SHIN ,  Junyeong HEO

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

公开(公告)号：US20170201013A1

公开(公告)日：2017-07-13

申请号：US15375778

申请日：2016-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wowjin CHOI ,  Sungkee KIM ,  Dongryul SHIN ,  Junhyuck LEE ,  Sooyoung JANG ,  Moonhyuk CHOI ,  Kwangho KIM ,  Joonbo PARK ,  Hanjae BAE ,  Seunghun SHIN ,  Chulhyung YANG ,  Jiwoo LEE

IPC: H01Q1/24 ,  H01Q1/50 ,  H01Q1/38 ,  H01Q1/48

CPC classification number: H01Q1/243 ,  H01Q1/38 ,  H01Q1/44 ,  H01Q1/48 ,  H01Q1/50 ,  H01Q1/521 ,  H01Q5/00 ,  H01Q9/00 ,  H01Q21/28

Abstract: An electronic device is provided including a housing including a first plate, a second plate facing the first plate, and a side member between the first and second plate, a radio frequency (RF) circuit, a processor, a ground member, a first electric path connected between a first port of the RF circuit and a first point of a first conductive portion of the side member, a second electric path connected between a second port of the RF circuit and a first point of a second conductive portion of the side member, a third electric path connected between a second point of the first conductive portion and the ground member, a fourth electric path connected between a second point of the second conductive portion and the ground member, and a fifth electric path connected between one point of the second electric path and one point of the third electric path.

公开(公告)号：US20190355671A1

公开(公告)日：2019-11-21

申请号：US16530993

申请日：2019-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae CHO ,  Sundae KIM ,  HYUNGGIL BAEK ,  Namgyu BAEK ,  Seunghun SHIN ,  Donghoon WON

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/58 ,  H01L21/02

Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.

公开(公告)号：US20240178191A1

公开(公告)日：2024-05-30

申请号：US18467330

申请日：2023-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihun JUNG ,  Unbyoung KANG ,  Yeongkwon KO ,  Seunghun SHIN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L23/481 ,  H01L24/08 ,  H10B80/00 ,  H01L2224/08146

Abstract: A semiconductor chip including a semiconductor substrate having an active surface and a non-active surface opposite to each other, a plurality of through electrodes passing through the semiconductor substrate, a plurality of wiring structures on the active surface and electrically connected to the plurality of through electrodes, an inter-wire insulating layer surrounding the plurality of wiring structures, a plurality of front chip connection pads electrically connected to the plurality of wiring structures, a front insulating layer surrounding the plurality of front chip connection pads, on the inter-wire insulating layer, a plurality of rear chip connection pads disposed on the non-active surface and electrically connected to the plurality of through electrodes, and a rear insulating layer surrounding the plurality of rear chip connection pads, on the non-active surface, wherein the front insulating layer includes a cover insulating portion covering a side surface of the inter-wire insulating layer may be provided.

公开(公告)号：US20240379478A1

公开(公告)日：2024-11-14

申请号：US18780720

申请日：2024-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Seunghun SHIN ,  Junyeong HEO

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

公开(公告)号：US20180261555A1

公开(公告)日：2018-09-13

申请号：US15850336

申请日：2017-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae CHO ,  Sundae KIM ,  Hyunggil Baek ,  Namgyu BAEK ,  Seunghun SHIN ,  Donghoon WON

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/02

Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.