公开(公告)号：US12272606B2

公开(公告)日：2025-04-08

申请号：US18300983

申请日：2023-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmin Yoo ,  Juyoun Kim ,  Hyungjoo Na ,  Bongseok Suh ,  Jooho Jung ,  Euichul Hwang ,  Sungmoon Lee

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/118

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

公开(公告)号：US12243785B2

公开(公告)日：2025-03-04

申请号：US18425390

申请日：2024-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

公开(公告)号：US12046650B2

公开(公告)日：2024-07-23

申请号：US17120784

申请日：2020-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Sangjung Kang ,  Jinwoo Kim ,  Jihwan An ,  Seulgi Yun

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L29/42364 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4238 ,  H01L29/495

Abstract: A semiconductor device includes a substrate having a first, a second, a third, and a fourth region; a first gate structure in the first region and including a first gate dielectric layer, and a first, a second, and a third conductive layer; a second gate structure in the second region and including a second gate dielectric layer, and the second and the third conductive layer; a third gate structure in the third region and including a third gate dielectric layer, and the second and the third conductive layer; and a fourth gate structure in the fourth region and including the second gate dielectric layer, and a fourth and the third conductive layer. The first gate dielectric layer includes a material of the second gate dielectric layer and a first element, and the third gate dielectric layer includes a material of the second gate dielectric layer and a second element.

公开(公告)号：US10734288B2

公开(公告)日：2020-08-04

申请号：US16459889

申请日：2019-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L27/092 ,  H01L27/088 ,  H01L21/28 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

公开(公告)号：US20240282835A1

公开(公告)日：2024-08-22

申请号：US18649646

申请日：2024-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyoun Kim ,  Hyung Jong Lee ,  Seulgi Yun ,  Seki Hong

IPC: H01L29/423 ,  H01L27/092

CPC classification number: H01L29/42372 ,  H01L27/0924

Abstract: A semiconductor device includes a first active pattern on a substrate. The first active pattern includes a pair of first source/drain patterns and a first channel pattern therebetween. A gate electrode is disposed on the first channel pattern, and a first gate spacer is disposed on a side surface of the gate electrode. The first gate spacer includes a first spacer and a second spacer. A top surface of the first spacer is lower than a top surface of the second spacer. A first blocking pattern is disposed on the first spacer, and a gate contact is coupled to the gate electrode. The first blocking pattern is interposed between the gate contact and the second spacer.

公开(公告)号：US11362187B2

公开(公告)日：2022-06-14

申请号：US16950104

申请日：2020-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Jinwoo Kim ,  Kyuman Hwang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes first and second active regions on a substrate, an element isolation layer between the first and second active regions, a dummy gate line, dummy gate spacers at opposite side walls of the dummy gate line, and a dummy gate capping layer on the dummy gate line and. An upper surface of the element isolation layer is proximate to an upper surface of the substrate in relation to an upper end of the first active region in a vertical direction. The dummy gate line includes a horizontal section extending on the first active region to the element isolation layer in a horizontal direction, and a vertical section extending downwards from the horizontal section along a side wall of the first active region, the dummy gate line having an L shape, a vertical thickness of the horizontal section being smaller than a vertical thickness of the vertical section.

公开(公告)号：US10651172B2

公开(公告)日：2020-05-12

申请号：US16174702

申请日：2018-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taewon Ha ,  Juyoun Kim ,  Sang Min Lee ,  Moon-Sun Hong ,  Seki Hong

IPC: H01L27/088 ,  H01L21/28 ,  H01L29/51 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes a substrate having an active region, and first to third transistors on the active region of the substrate, each of the first to third transistors including a dielectric layer on the substrate, a metal layer on the dielectric layer, a barrier layer between the dielectric layer and the metal layer, and a work function layer between the dielectric layer and the barrier layer, wherein the barrier layer of the third transistor is in contact with the dielectric layer of the third transistor, and wherein a threshold voltage of the second transistor is greater than a threshold voltage of the first transistor and less than a threshold voltage of the third transistor.

公开(公告)号：US20190326181A1

公开(公告)日：2019-10-24

申请号：US16459889

申请日：2019-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L27/092 ,  H01L27/088 ,  H01L29/51 ,  H01L29/49

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

公开(公告)号：US20240304568A1

公开(公告)日：2024-09-12

申请号：US18595666

申请日：2024-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inyeal Lee ,  Younghoi Kim ,  Juyoun Kim ,  Jaekang Park

IPC: H01L23/00 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L23/562 ,  H01L21/823878 ,  H01L27/092

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of gate structures which are spaced apart from each other in a first horizontal direction on the semiconductor substrate and extend in a second horizontal direction perpendicular to the first horizontal direction, and a single diffusion brake which extends in the second horizontal direction between the plurality of gate structures and is located in a first trench having a first depth in a vertical direction. The single diffusion brake includes a lower insulating material film conformally disposed on a side wall of the first trench, an insulating liner extending onto upper surfaces of the plurality of gate structures along an inner wall of the lower insulating material film, and an upper insulating material film disposed on the insulating liner and filling the inside of the first trench.

公开(公告)号：US11978779B2

公开(公告)日：2024-05-07

申请号：US17580847

申请日：2022-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyoun Kim ,  Hyung Jong Lee ,  Seulgi Yun ,  Seki Hong

IPC: H01L29/423 ,  H01L27/092

CPC classification number: H01L29/42372 ,  H01L27/0924

Abstract: A semiconductor device includes a first active pattern on a substrate. The first active pattern includes a pair of first source/drain patterns and a first channel pattern therebetween. A gate electrode is disposed on the first channel pattern, and a first gate spacer is disposed on a side surface of the gate electrode. The first gate spacer includes a first spacer and a second spacer. A top surface of the first spacer is lower than a top surface of the second spacer. A first blocking pattern is disposed on the first spacer, and a gate contact is coupled to the gate electrode. The first blocking pattern is interposed between the gate contact and the second spacer.