公开(公告)号：US20250169174A1

公开(公告)日：2025-05-22

申请号：US18790772

申请日：2024-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyuman Hwang ,  Jinho Bae ,  Jaewon Jeong ,  Sungil Park

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a lower transistor and an upper transistor located at a higher vertical level than the lower transistor. The lower transistor includes a lower source/drain region, and a lower gate structure and a lower isolation insulating layer that are in contact with a side surface of the lower source/drain region. The upper transistor includes an upper source/drain region, and an upper gate structure and an upper isolation insulating layer that are in contact with a side surface of the upper source/drain region. A bottom surface of the lower isolation insulating layer is located at a same vertical level as a bottom surface of the lower gate structure.

公开(公告)号：US12218133B2

公开(公告)日：2025-02-04

申请号：US17805261

申请日：2022-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungil Park ,  Jae Hyun Park ,  Daewon Ha ,  Kyuman Hwang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Provided is a three-dimensional semiconductor device and its fabrication method. The semiconductor device includes a first active region on a substrate and including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction, a second active region on the first active region and including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction, a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns, and a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns. The second gate electrode may include lower and upper gate electrodes with an isolation pattern interposed therebetween.

公开(公告)号：US20240282864A1

公开(公告)日：2024-08-22

申请号：US18432351

申请日：2024-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkyu Lee ,  Sungil Park ,  Jaehyun Park ,  Jinwook Yang ,  Jinchan Yun ,  Cheoljin Yun ,  Daewon Ha ,  Kyuman Hwang

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: An integrated circuit semiconductor device with three dimensional transistors includes two gate-all-around transistors or multi-bridge channel field effect transistors may be vertically stacked to reduce unit area. The two stacked transistors may be separated by an isolation insulating layer. The two stacked transistors may be positioned on two opposite sides of the isolation insulating layer, with the structure of the two stacked transistors positioned in an opposite manner. According to embodiments of the present disclosure, metal wiring layers may be connected to the two stacked transistors at their far ends, away from the isolation insulating layer. A method for manufacturing an integrated circuit semiconductor device according to the present disclosure is described. Accordingly, aspects described herein may result in reduced unit area and easy manufacture of metal wiring layer connected to the transistors.

公开(公告)号：US11362187B2

公开(公告)日：2022-06-14

申请号：US16950104

申请日：2020-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun Kim ,  Jinwoo Kim ,  Kyuman Hwang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes first and second active regions on a substrate, an element isolation layer between the first and second active regions, a dummy gate line, dummy gate spacers at opposite side walls of the dummy gate line, and a dummy gate capping layer on the dummy gate line and. An upper surface of the element isolation layer is proximate to an upper surface of the substrate in relation to an upper end of the first active region in a vertical direction. The dummy gate line includes a horizontal section extending on the first active region to the element isolation layer in a horizontal direction, and a vertical section extending downwards from the horizontal section along a side wall of the first active region, the dummy gate line having an L shape, a vertical thickness of the horizontal section being smaller than a vertical thickness of the vertical section.

公开(公告)号：US20240321960A1

公开(公告)日：2024-09-26

申请号：US18613324

申请日：2024-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinchan Yun ,  Sungil Park ,  Jaehyun Park ,  Dongkyu Lee ,  Kyuman Hwang

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A multi-stack semiconductor device includes a substrate, a device isolation layer, first channels, first gate lines covering the first channel, extending in a second horizontal direction, and spaced apart from each other in the first horizontal direction, first source/drain areas arranged on both sides of each of the first channels in the first horizontal direction, a second channel arranged apart from the first gate line in the vertical direction over any one of the first gate lines, a second gate line, second source/drain areas, a third channel arranged apart from the second gate line in the vertical direction over the second gate line, a third gate line, third source/drain areas, and a first lower source/drain contact extending in the vertical direction and connected to each of the first source/drain area, the second source/drain area, and the third source/drain area.

公开(公告)号：US20230039722A1

公开(公告)日：2023-02-09

申请号：US17694011

申请日：2022-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doyoung CHOI ,  Daewon Ha ,  Kyungho Kim ,  Mingyu Kim ,  Kyuman Hwang

IPC: H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes: a substrate including first and second regions, first and second active patterns in the first and second regions, respectively; first source/drain patterns and a first channel pattern including first semiconductor patterns; second source/drain patterns and a second channel pattern including second semiconductor patterns; first and second gate electrodes on the first and second channel patterns, respectively; and a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer includes a first interface layer between the first channel pattern and the first gate electrode, and a first high-k dielectric layer. The second gate dielectric layer includes a second interface layer and a second high-k dielectric layer between the second channel pattern and the second gate electrode. A thickness of the first high-k dielectric layer is greater than that of the second high-k dielectric layer. A thickness of the first semiconductor pattern is less than that of the second semiconductor pattern