公开(公告)号：US10193562B2

公开(公告)日：2019-01-29

申请号：US15802601

申请日：2017-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangyeop Choo ,  Wonsik Yu ,  Wooseok Kim ,  Jihyun Kim ,  Taeik Kim ,  Hyunik Kim

IPC: H03D3/24 ,  H03L7/107 ,  H03L7/099 ,  H03L7/199 ,  H03L7/18 ,  H03L7/087 ,  H03L7/091

Abstract: A digital phase locked loop circuit includes a phase frequency detector, a bandwidth calibrator, a digital loop filter, and a digital controlled oscillator. The phase frequency detector generates a first detection value and a second detection value of which each is associated with order between a phase of a reference signal and a phase of a fed-back signal. The bandwidth calibrator amplifies a signal level of the second detection value by a gain value to generate an amplified detection value, and adjusts the gain value based on the first detection value. The digital loop filter generates a digital code based on the amplified detection value. The digital controlled oscillator generates an output signal having a frequency which corresponds to the digital code. The fed-back signal is generated based on the output signal and is fed back to the phase frequency detector.

公开(公告)号：US11700005B2

公开(公告)日：2023-07-11

申请号：US17509540

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangyeop Choo ,  Insung Kim ,  Wooseok Kim ,  Taeik Kim ,  Sunghyuck Lee ,  Chanyoung Jeong

IPC: H03L7/089 ,  H03L7/10

CPC classification number: H03L7/0891 ,  H03L7/101

Abstract: A phased locked loop includes; a load circuit that generates an output signal in response to a driving voltage, a frequency calibration circuit that generates a calibration signal in response to an output frequency of the output signal and a target frequency, and a regulator that generates the driving voltage in response to the calibration signal.

公开(公告)号：US20180375523A1

公开(公告)日：2018-12-27

申请号：US15861962

申请日：2018-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsik Yu ,  Wooseok Kim ,  Jihyun Kim ,  Taeik Kim ,  Kangyeop Choo

IPC: H03L7/095 ,  H03K5/135 ,  H03L7/18

Abstract: A digital phase locked loop includes a digital phase detector, a digital loop filter, a digital controlled oscillator, a first divider that divides the second frequency of the oscillation signal depending on a first division value and outputs the division result as a division signal having a third frequency, a second divider that divides the second frequency of the oscillation signal depending on a second division value and outputs the division result as an output signal having a final frequency, a dithering block that receives the division signal and performs dithering on the first division value based on a preset pattern as cycles of the division signal pass, and a digital phase domain filter that performs second low pass filtering on the division signal in a phase domain and outputs the result of the second low pass filtering as the feedback signal.

公开(公告)号：US11736112B2

公开(公告)日：2023-08-22

申请号：US17675351

申请日：2022-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangyeop Choo ,  Wooseok Kim ,  Wonsik Yu ,  Chanyoung Jeong

IPC: H03L7/099 ,  H03B5/04 ,  H03L7/093

CPC classification number: H03L7/0992 ,  H03B5/04 ,  H03L7/093

Abstract: A digitally controlled oscillator (DCO) includes; a current mirror configured to generate a supply current in response to a bias voltage matching a reference current, a variable resistor connected to the current mirror through a first node outputting the reference current and configured to provide a variable resistance in response to a first control signal, an oscillation circuit connected to the current mirror through a second node outputting the supply current and configured to generate an oscillation signal in response to the supply current, and a feedback circuit configured to control the bias voltage in relation to at least one of a voltage at the first node and a voltage at the second node.

公开(公告)号：US10158367B1

公开(公告)日：2018-12-18

申请号：US15861962

申请日：2018-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsik Yu ,  Wooseok Kim ,  Jihyun Kim ,  Taeik Kim ,  Kangyeop Choo

IPC: H03L7/18 ,  H03L7/23 ,  H03L7/095 ,  H03K5/135

CPC classification number: H03L7/235 ,  H03K5/135 ,  H03L7/095 ,  H03L7/18 ,  H03L2207/08

Abstract: A digital phase locked loop includes a digital phase detector, a digital loop filter, a digital controlled oscillator, a first divider that divides the second frequency of the oscillation signal depending on a first division value and outputs the division result as a division signal having a third frequency, a second divider that divides the second frequency of the oscillation signal depending on a second division value and outputs the division result as an output signal having a final frequency, a dithering block that receives the division signal and performs dithering on the first division value based on a preset pattern as cycles of the division signal pass, and a digital phase domain filter that performs second low pass filtering on the division signal in a phase domain and outputs the result of the second low pass filtering as the feedback signal.