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    CLOCK GENERATION CIRCUITS AND METHODS OF GENERATING CLOCK SIGNALS
    1.
    发明申请
    CLOCK GENERATION CIRCUITS AND METHODS OF GENERATING CLOCK SIGNALS 有权

    公开(公告)号：US20220239284A1

    公开(公告)日：2022-07-28

    申请号：US17466006

    申请日：2021-09-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wonsik Yu ,  Wooseok Kim ,  Taeik Kim ,  Chanyoung Jeong

    IPC: H03K3/011 ,  H03K3/037 ,  G06F1/08 ,  G06F1/12

    Abstract: A clock generation circuit includes a temperature compensation circuit and an oscillator. The temperature compensation circuit is configured to generate a temperature-compensated frequency selection code that varies depending on an operation temperature based on a difference between the operation temperature and a reference temperature and based on a temperature-independent frequency selection code that is fixed regardless of the operation temperature. The oscillator is configured to generate a clock signal that has an operation frequency that is based on the temperature-compensated frequency selection code, such that the operation frequency is uniform regardless of the operation temperature. Effects of the operation temperature may be reduced by generating the temperature-compensated frequency selection code that reflects the temperature characteristic of the oscillator using the output value of the temperature sensor and by controlling the oscillator using the temperature-compensated frequency selection code.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20230086367A1

    公开(公告)日：2023-03-23

    申请号：US17731464

    申请日：2022-04-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jisu Yu ,  Youngsook Do ,  Eunsung Seo ,  Wooseok Kim ,  Wonsik Yu ,  Chanyoung Jeong

    IPC: H01L23/528 ,  H01L23/522

    Abstract: A semiconductor device includes: a standard cell array including a plurality of standard cells, each of the plurality of standard cells; a plurality of power supply lines configured to provide a power supply voltage and extending in a first direction; a capacitor structure including electrode structures included in each of a plurality of dielectric layers formed on the standard cell array, the capacitor structure having vias connecting the electrode structures; and contacts electrically connecting the capacitor structure and the standard cell array to each other. Each of the plurality of standard cells provides a unit capacitor circuit having capacitance that is based on a connection structure of active regions and gates of first and second transistors thereof.

    OSCILLATION SYSTEM INCLUDING FREQUENCY-LOCKED LOOP LOGIC CIRCUIT AND OPERATING METHOD THEREOF
    4.
    发明申请
    OSCILLATION SYSTEM INCLUDING FREQUENCY-LOCKED LOOP LOGIC CIRCUIT AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20230009620A1

    公开(公告)日：2023-01-12

    申请号：US17860519

    申请日：2022-07-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jusung LEE ,  Wooseok Kim ,  Wonsik Yu ,  Chanyoung Jeong

    IPC: H03L7/099 ,  H03L7/07 ,  H03L7/091 ,  H03L7/18

    Abstract: A frequency-locked loop (FLL) logic circuit, including a validity signal generator configured to receive an external clock signal and determine whether a glitch occurs in the external clock signal; a clock divider configured to generate a reference frequency clock signal based on the external clock signal and a determination result of the validity signal generator; a synchronizer configured to synchronize a phase of an oscillator clock signal with a phase of the reference frequency clock signal; a clock counter configured to count a number of pulses of the oscillator clock signal during a reference time; and a code limiter configured to determine a range of a frequency selection value for calibrating an operating frequency of the oscillator clock signal based on the counted number of pulses.

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