公开(公告)号：US20230352547A1

公开(公告)日：2023-11-02

申请号：US18107793

申请日：2023-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongsik Shin ,  Sungwoo Kang ,  Dongkwon Kim ,  Hyonwook Ra ,  Jeongyeon Seo ,  Kyungyub Jeon

IPC: H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L29/41775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes first and second gate structures, first and second contact plug structures and a first wiring on a substrate. The first and second source/drain layers are formed on portions of the substrate adjacent to the first and second gate structures, respectively. The first and second contact plug structures are formed on the first and second source/drain layers, respectively. The first wiring contacts an upper surface of the first gate structure. The first gate structure includes a first gate electrode and a first gate insulation pattern on a lower surface and a sidewall of the first gate electrode. The second gate structure includes a second gate electrode and a second gate insulation pattern on a lower surface and a sidewall of the second gate electrode. The upper surface of the second gate electrode is lower than an upper surface of the first gate electrode.

公开(公告)号：US10593596B2

公开(公告)日：2020-03-17

申请号：US15959319

申请日：2018-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwoo Han ,  Kwang-Yong Yang ,  Jinwook Lee ,  Kyungyub Jeon ,  Haegeon Jung ,  Dohyoung Kim

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/306

Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.

公开(公告)号：US09984931B2

公开(公告)日：2018-05-29

申请号：US15260952

申请日：2016-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwoo Han ,  Kwang-Yong Yang ,  Jinwook Lee ,  Kyungyub Jeon ,  Haegeon Jung ,  Dohyoung Kim

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/306

CPC classification number: H01L21/823431 ,  H01L21/30604 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.