公开(公告)号：US12014904B2

公开(公告)日：2024-06-18

申请号：US17370766

申请日：2021-07-08

申请人： Samsung Electronics Co., Ltd.

发明人： Jongchul Park ,  Hyonwook Ra

IPC分类号： H01J37/32 ,  H01L21/3213

CPC分类号： H01J37/32568 ,  H01J37/32422 ,  H01J37/32715 ,  H01J37/32082 ,  H01J2237/2007 ,  H01L21/32136

摘要： A wafer processing apparatus is provided. The wafer processing apparatus includes a chamber body defining a plasma region configured that plasma is generated in the plasma region, a wafer support arranged in the chamber body and configured to support a wafer, first and second electrodes arranged between the wafer support and the plasma region and having apertures configured to guide a path of ions of the plasma, a first power source configured to apply, to the first electrode, a voltage that is higher than a voltage applied to the second electrode, and a second power source configured to apply, to the wafer support, a voltage that is higher than the voltage applied to the second electrode.

公开(公告)号：US20230352547A1

公开(公告)日：2023-11-02

申请号：US18107793

申请日：2023-02-09

申请人： Samsung Electronics Co., Ltd.

发明人： Hongsik Shin ,  Sungwoo Kang ,  Dongkwon Kim ,  Hyonwook Ra ,  Jeongyeon Seo ,  Kyungyub Jeon

IPC分类号： H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L29/775 ,  H01L29/423

CPC分类号： H01L29/41775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

摘要： A semiconductor device includes first and second gate structures, first and second contact plug structures and a first wiring on a substrate. The first and second source/drain layers are formed on portions of the substrate adjacent to the first and second gate structures, respectively. The first and second contact plug structures are formed on the first and second source/drain layers, respectively. The first wiring contacts an upper surface of the first gate structure. The first gate structure includes a first gate electrode and a first gate insulation pattern on a lower surface and a sidewall of the first gate electrode. The second gate structure includes a second gate electrode and a second gate insulation pattern on a lower surface and a sidewall of the second gate electrode. The upper surface of the second gate electrode is lower than an upper surface of the first gate electrode.

公开(公告)号：US10553593B2

公开(公告)日：2020-02-04

申请号：US15983405

申请日：2018-05-18

申请人： Samsung Electronics Co., Ltd.

发明人： Deokhan Bae ,  Hyonwook Ra ,  Hyung Jong Lee ,  Juhun Park

IPC分类号： H01L27/11 ,  H01L23/522 ,  G11C11/412 ,  H01L27/092

摘要： A semiconductor device includes a substrate including active patterns, a device isolation layer filling a trench between a pair of adjacent active patterns, a gate electrode on the active patterns, and a gate contact on the gate electrode. Each active pattern includes source/drain patterns at opposite sides of the gate electrode. The gate contact includes a first portion vertically overlapping with the gate electrode, and a second portion laterally extending from the first portion such that the second portion vertically overlaps with the device isolation layer and does not vertically overlap with the gate electrode. A bottom surface of the second portion is distal to the substrate in relation to a bottom surface of the first portion. The bottom surface of the second portion is distal to the substrate in relation to a top of a source/drain pattern that is adjacent to the second portion.

公开(公告)号：US20240243064A1

公开(公告)日：2024-07-18

申请号：US18453546

申请日：2023-08-22

申请人： Samsung Electronics Co., Ltd.

发明人： Jeongyeon Seo ,  Sungwoo Kang ,  Hyonwook Ra ,  Hongsik Shin

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC分类号： H01L23/5286 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

摘要： An integrated circuit device includes a fin-type active region that extends from a substrate and in a first lateral direction, a device isolation film on a trench region on the substrate, an insulating liner structure that extends through the substrate in a vertical direction and contacts the device isolation film at a first vertical level, a via power rail that extends through the device isolation film in the vertical direction and comprising a first bottom surface at a second vertical level, and a backside power rail comprising a main rail and a protrusion rail, where the main rail extends through the substrate and the insulating liner structure in the vertical direction, and where the protrusion rail extends from the main rail toward the via power rail.

公开(公告)号：US20230116172A1

公开(公告)日：2023-04-13

申请号：US17935714

申请日：2022-09-27

申请人： Samsung Electronics Co., Ltd.

发明人： Jongchul Park ,  Hyonwook Ra

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

摘要： A semiconductor device includes active regions including first and second active regions parallel to each other and extending in a first direction, gate structures including first gate structures intersecting the first active region, extending in a second direction, and parallel to each other, and second gate structures intersecting the second active region, and opposite the first gate structures in the second direction, a gate isolation pattern between the first and second gate structures, a source/drain region on at least one side of the gate structures, and a common contact plug electrically connected to the source/drain region, wherein the gate isolation pattern includes a lower region and upper regions extending from the lower region in a third direction and spaced apart from each other in the first direction, wherein the upper regions are between the first and second gate structures.

公开(公告)号：US20220172930A1

公开(公告)日：2022-06-02

申请号：US17370766

申请日：2021-07-08

申请人： Samsung Electronics Co., Ltd.

发明人： Jongchul Park ,  Hyonwook Ra

IPC分类号： H01J37/32

摘要： A wafer processing apparatus is provided. The wafer processing apparatus includes a chamber body defining a plasma region configured that plasma is generated in the plasma region, a wafer support arranged in the chamber body and configured to support a wafer, first and second electrodes arranged between the wafer support and the plasma region and having apertures configured to guide a path of ions of the plasma, a first power source configured to apply, to the first electrode, a voltage that is higher than a voltage applied to the second electrode, and a second power source configured to apply, to the wafer support, a voltage that is higher than the voltage applied to the second electrode.