公开(公告)号：US12148701B2

公开(公告)日：2024-11-19

申请号：US18594816

申请日：2024-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik Shin ,  Sanghyun Lee ,  Hakyoon Ahn ,  Seonghan Oh ,  Youngmook Oh

IPC: H01L23/532 ,  H01L21/308 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/66 ,  H01L49/02 ,  H01L29/165

Abstract: A semiconductor device including a metal pattern on a semiconductor substrate; an etch stop layer covering the metal pattern, the etch stop layer including a sequentially stacked first insulation layer, second insulation layer, and third insulation layer; an interlayer dielectric layer on the etch stop layer; and a contact plug penetrating the interlayer dielectric layer and the etch stop layer, the contact plug being connected to the metal pattern, wherein the first insulation layer includes a first insulating material that contains a metallic element and nitrogen, wherein the second insulation layer includes a second insulating material that contains carbon, and wherein the third insulation layer includes a third insulating material that does not contain a metallic element and carbon.

公开(公告)号：US11031340B2

公开(公告)日：2021-06-08

申请号：US16167717

申请日：2018-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongsik Shin ,  Sanghyun Lee ,  Hakyoon Ahn ,  Seonghan Oh ,  Youngmook Oh

IPC: H01L23/58 ,  H01L23/532 ,  H01L21/768 ,  H01L29/66 ,  H01L21/308 ,  H01L27/088 ,  H01L49/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/165

Abstract: A semiconductor device including a metal pattern on a semiconductor substrate; an etch stop layer covering the metal pattern, the etch stop layer including a sequentially stacked first insulation layer, second insulation layer, and third insulation layer; an interlayer dielectric layer on the etch stop layer; and a contact plug penetrating the interlayer dielectric layer and the etch stop layer, the contact plug being connected to the metal pattern, wherein the first insulation layer includes a first insulating material that contains a metallic element and nitrogen, wherein the second insulation layer includes a second insulating material that contains carbon, and wherein the third insulation layer includes a third insulating material that does not contain a metallic element and carbon.

公开(公告)号：US12068242B2

公开(公告)日：2024-08-20

申请号：US17373900

申请日：2021-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik Shin ,  Dong Kwon Kim ,  Jinwook Lee ,  Jongchul Park ,  Wonhyuk Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L23/5226 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device including a gate pattern on a substrate and including a gate dielectric layer, a gate electrode, and a gate capping pattern that are sequentially stacked; a gate spacer on a sidewall of the gate pattern; a source/drain pattern in the substrate; a contact pad on the source/drain pattern, a source/drain contact on the contact pad; and a buried dielectric pattern between the gate spacer and the source/drain contact, wherein the gate spacer includes a first segment between the gate electrode and the source/drain pattern; a second segment that extends from the first segment and between the gate electrode and the source/drain contact; and a third segment on the second segment, the buried dielectric pattern is between the third segment and the source/drain contact, and is absent between the first segment and the contact pad and is absent between the second segment and the source/drain contact.

公开(公告)号：US20240243064A1

公开(公告)日：2024-07-18

申请号：US18453546

申请日：2023-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongyeon Seo ,  Sungwoo Kang ,  Hyonwook Ra ,  Hongsik Shin

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: An integrated circuit device includes a fin-type active region that extends from a substrate and in a first lateral direction, a device isolation film on a trench region on the substrate, an insulating liner structure that extends through the substrate in a vertical direction and contacts the device isolation film at a first vertical level, a via power rail that extends through the device isolation film in the vertical direction and comprising a first bottom surface at a second vertical level, and a backside power rail comprising a main rail and a protrusion rail, where the main rail extends through the substrate and the insulating liner structure in the vertical direction, and where the protrusion rail extends from the main rail toward the via power rail.

公开(公告)号：US20230335606A1

公开(公告)日：2023-10-19

申请号：US18079057

申请日：2022-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Sangduk Park ,  Dongsoo Seo ,  Hongsik Shin ,  Jinwook Lee

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41775 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/7851 ,  H01L29/66795 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L29/66439

Abstract: A semiconductor device includes a gate structure on a substrate, a gate spacer on a sidewall of the gate structure, a source/drain layer on a portion of the substrate adjacent to the gate structure, and a first contact plug on the source/drain layer and contacting an outer sidewall of the gate spacer. The gate structure includes a first conductive pattern having a lower portion and an upper portion on the lower portion with a width greater than the lower portion and in contact with an inner sidewall of the gate spacer, a second conductive pattern on a lower surface and a sidewall of the lower portion of the first conductive pattern, and a gate insulating pattern on a lower surface and an outer sidewall of the second conductive pattern. An upper surface of the first conductive pattern is substantially coplanar with an upper surface of the first contact plug.

公开(公告)号：US12034060B2

公开(公告)日：2024-07-09

申请号：US17837158

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik Shin ,  Hyunjoon Roh ,  Heungsik Park ,  Sughyun Sung ,  Dohaing Lee ,  Wonhyuk Lee

IPC: H01L29/06 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

公开(公告)号：US20230352547A1

公开(公告)日：2023-11-02

申请号：US18107793

申请日：2023-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongsik Shin ,  Sungwoo Kang ,  Dongkwon Kim ,  Hyonwook Ra ,  Jeongyeon Seo ,  Kyungyub Jeon

IPC: H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L29/41775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes first and second gate structures, first and second contact plug structures and a first wiring on a substrate. The first and second source/drain layers are formed on portions of the substrate adjacent to the first and second gate structures, respectively. The first and second contact plug structures are formed on the first and second source/drain layers, respectively. The first wiring contacts an upper surface of the first gate structure. The first gate structure includes a first gate electrode and a first gate insulation pattern on a lower surface and a sidewall of the first gate electrode. The second gate structure includes a second gate electrode and a second gate insulation pattern on a lower surface and a sidewall of the second gate electrode. The upper surface of the second gate electrode is lower than an upper surface of the first gate electrode.

公开(公告)号：US11362196B2

公开(公告)日：2022-06-14

申请号：US16841889

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik Shin ,  Hyunjoon Roh ,  Heungsik Park ,  Sughyun Sung ,  Dohaing Lee ,  Wonhyuk Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L29/78 ,  H01L21/768 ,  H01L21/311 ,  H01L21/306 ,  H01L21/8234

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

公开(公告)号：US09536983B2

公开(公告)日：2017-01-03

申请号：US14970710

申请日：2015-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Young Lee ,  Dohyoung Kim ,  Johnsoo Kim ,  Heungsik Park ,  Hongsik Shin ,  Younghun Choi

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/6656 ,  H01L29/401 ,  H01L29/4232 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming a gate electrode on a substrate, forming a first spacer on a sidewall of the gate electrode, forming a second spacer on the first spacer, and forming a capping pattern on top surfaces of the gate electrode, the first spacer and the second spacer. An outer sidewall of the second spacer is vertically aligned with a sidewall of the capping pattern.

Abstract translation: 形成半导体器件的方法包括在衬底上形成栅电极，在栅电极的侧壁上形成第一间隔物，在第一间隔物上形成第二间隔物，并在栅电极的顶表面上形成封盖图案， 第一间隔物和第二间隔物。 第二间隔件的外侧壁与封盖图案的侧壁垂直对齐。

公开(公告)号：US12284821B2

公开(公告)日：2025-04-22

申请号：US17849797

申请日：2022-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghwan Chun ,  Hongsik Shin ,  Koungmin Ryu ,  Bongkwan Baek ,  Jongmin Baek

IPC: H10D30/67 ,  H01L21/02 ,  H10D30/01 ,  H10D30/43 ,  H10D62/10 ,  H10D64/01

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction, a gate structure including a gate electrode extending on the substrate in a second direction and traversing the active region, a spacer structure extending on opposing sidewalls of the gate electrode in the second direction, and a capping layer on the gate electrode and the spacer structure, a source/drain region on the active region adjacent the gate structure, and a first contact plug connected to the source/drain region and a second contact plug connected to the gate structure. The capping layer includes a lower capping layer and an upper capping layer on the lower capping layer, and the second contact plug penetrates through the capping layer, is connected to the gate electrode and includes a convex sidewall penetrating into the upper capping layer.