公开(公告)号：US20240192712A1

公开(公告)日：2024-06-13

申请号：US18468613

申请日：2023-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEONJUN YUN ,  SANGSU YEH ,  MINSU LEE ,  JONGHWA KIM ,  JOOYEOP NAM

IPC: G05D23/19 ,  H01L21/683

CPC classification number: G05D23/1931 ,  H01L21/6833

Abstract: A temperature control system of a semiconductor manufacturing device includes first and second heating media storages that respectively store low-temperature heating media and high-temperature heating media, a mixing device including a mixing valve that mixes the low-temperature heating media and the high-temperature heating media at a predetermined mixing ratio, and a control device. The mixing device provides mixed heating media to a load, and distributes recovered heating media recovered from the load to the first and second heating media storages. The control device is configured to, by performing feed-forward control and feedback control over a mixing unit temperature using a relationship model between a reference temperature representing a temperature of heating media passing through the load and the mixing unit temperature which is a temperature of heating media output by the mixing valve, control the mixing ratio such that the reference temperature has a target reference temperature.

公开(公告)号：US20220246180A1

公开(公告)日：2022-08-04

申请号：US17481583

申请日：2021-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： WONSOK LEE ,  MIN TAE RYU ,  WOO BIN SONG ,  KISEOK LEE ,  MINSU LEE ,  MIN HEE CHO

IPC: G11C5/06 ,  H01L29/06 ,  H01L27/108

Abstract: A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

公开(公告)号：US20220013525A1

公开(公告)日：2022-01-13

申请号：US17172124

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： MIN HEE CHO ,  HYUNMOG PARK ,  WOO BIN SONG ,  MINSU LEE ,  WONSOK LEE

IPC: H01L27/108

Abstract: A semiconductor memory device is provided. The device may include a lower gate line provided on a substrate and extended in a first direction, an upper gate line vertically overlapped with the lower gate line and extended in the first direction, a first capacitor provided between the lower gate line and the upper gate line, a second capacitor provided between the lower gate line and the upper gate line and spaced apart from the first capacitor in the first direction, a lower semiconductor pattern provided to penetrate the lower gate line and connected to the first capacitor, an upper semiconductor pattern provided to penetrate the upper gate line and connected to the second capacitor, and a lower insulating pattern provided between the second capacitor and the lower gate line to cover the entire region of a bottom surface of the second capacitor.