公开(公告)号：US20230187548A1

公开(公告)日：2023-06-15

申请号：US17976955

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： WONSOK LEE ,  MIN TAE RYU ,  SUNGWON YOO ,  KISEOK LEE ,  MIN HEE CHO

IPC: H01L29/78 ,  G11C5/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/105

CPC classification number: H01L29/7827 ,  G11C5/063 ,  H01L27/1052 ,  H01L29/0847 ,  H01L29/1033

Abstract: A semiconductor memory device includes bit lines disposed on a substrate and extending in a first direction in parallel to each other, a hydrogen supply insulating layer including hydrogen and filling a space between the bit lines, a source pattern located on each of the bit lines and being in partial contact with the hydrogen supply insulating layer, a hydrogen diffusion barrier layer covering a top surface of the hydrogen supply insulating layer and being in contact with a side surface of the source pattern, a first channel pattern located on the source pattern, a first word line being adjacent to a side surface of the first channel pattern and crossing over the bit lines, and a landing pad on the first channel pattern.

公开(公告)号：US20220246180A1

公开(公告)日：2022-08-04

申请号：US17481583

申请日：2021-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： WONSOK LEE ,  MIN TAE RYU ,  WOO BIN SONG ,  KISEOK LEE ,  MINSU LEE ,  MIN HEE CHO

IPC: G11C5/06 ,  H01L29/06 ,  H01L27/108

Abstract: A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

公开(公告)号：US20230337413A1

公开(公告)日：2023-10-19

申请号：US17981719

申请日：2022-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： MIN HEE CHO ,  MIN TAE RYU ,  Huije Ryu ,  SUNGWON YOO ,  Yongjin Lee ,  WONSOK LEE

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/10814 ,  G11C5/063 ,  H01L27/10897 ,  H01L27/10888 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891

Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a peripheral circuit structure including peripheral circuits on a semiconductor substrate and a first dielectric layer on the peripheral circuits, a cell array structure on the semiconductor substrate, and a shield layer between the peripheral circuit structure and the cell array structure. The cell array structure includes bit lines, first and second active patterns on the bit lines, first word lines that extend in a second direction on the first active patterns, second word lines that extend in the second direction on the second active patterns, data storage patterns on the first and second active patterns, and a second dielectric layer on the semiconductor substrate. A hydrogen concentration of the first dielectric layer is greater than that of the second dielectric layer.