公开(公告)号：US20190214293A1

公开(公告)日：2019-07-11

申请号：US16028794

申请日：2018-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu Jin Kim ,  Min Su Choi ,  Sung Hee Han ,  Bong Soo Kim ,  Yoo Sang Hwang

IPC: H01L21/762 ,  H01L27/108

CPC classification number: H01L21/76229 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a cell region and a peripheral region having different active region densities, forming cell trenches for limiting cell active regions in the cell region so that the cell active regions are formed to be spaced apart by a first width in a first direction and by a second width in a second direction, forming peripheral trenches for limiting a peripheral active region in the peripheral region, and forming, in the cell trenches, a first insulating layer continuously extending in the first and second directions and contacting sidewalls of the cell active regions, and having a thickness equal to or greater than half of the first width and less than half of the second width.

公开(公告)号：US20180108662A1

公开(公告)日：2018-04-19

申请号：US15835071

申请日：2017-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Hee Cho ,  Woo Song Ahn ,  Min Su Choi ,  Satoru Yamada ,  Jun Soo Kim ,  Sung Sam Lee

IPC: H01L27/108 ,  H01L29/51 ,  H01L29/423 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10876 ,  H01L28/90 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/51

Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.

公开(公告)号：US10199379B2

公开(公告)日：2019-02-05

申请号：US15835071

申请日：2017-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Hee Cho ,  Woo Song Ahn ,  Min Su Choi ,  Satoru Yamada ,  Jun Soo Kim ,  Sung Sam Lee

IPC: H01L29/51 ,  H01L27/108 ,  H01L49/02 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.

公开(公告)号：US09853031B1

公开(公告)日：2017-12-26

申请号：US15433193

申请日：2017-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Hee Cho ,  Woo Song Ahn ,  Min Su Choi ,  Satoru Yamada ,  Jun Soo Kim ,  Sung Sam Lee

IPC: H01L23/48 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L49/02

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10876 ,  H01L28/90 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/51

Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.