公开(公告)号：US11165018B2

公开(公告)日：2021-11-02

申请号：US16592041

申请日：2019-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Hwan Lee ,  Yong Seok Kim ,  Tae Hun Kim ,  Seok Han Park ,  Satoru Yamada ,  Jae Ho Hong

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.

公开(公告)号：US10886375B2

公开(公告)日：2021-01-05

申请号：US16288910

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin Lee ,  Junsoo Kim ,  Moonyoung Jeong ,  Satoru Yamada ,  Dongsoo Woo ,  Jiyoung Kim

IPC: H01L29/40 ,  H01L29/423 ,  H01L27/108 ,  H01L21/84 ,  H01L29/775 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/088

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

公开(公告)号：US20200161301A1

公开(公告)日：2020-05-21

申请号：US16726322

申请日：2019-12-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Uk Han ,  Taek Yong Kim ,  Satoru Yamada ,  Jun Hee Lim ,  Ki Jae Hur

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  G11C11/408

Abstract: A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.

公开(公告)号：US10431680B2

公开(公告)日：2019-10-01

申请号：US15391888

申请日：2016-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungsam Lee ,  Junsoo Kim ,  Hyoshin Ahn ,  Satoru Yamada ,  Joohyun Jeon ,  MoonYoung Jeong ,  Chunhyung Chung ,  Min Hee Cho ,  Kyo-Suk Chae ,  Eunae Choi

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/04

Abstract: A semiconductor device including a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.

公开(公告)号：US20180108662A1

公开(公告)日：2018-04-19

申请号：US15835071

申请日：2017-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Hee Cho ,  Woo Song Ahn ,  Min Su Choi ,  Satoru Yamada ,  Jun Soo Kim ,  Sung Sam Lee

IPC: H01L27/108 ,  H01L29/51 ,  H01L29/423 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10876 ,  H01L28/90 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/51

Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.

公开(公告)号：US20170084615A1

公开(公告)日：2017-03-23

申请号：US15204805

申请日：2016-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin Lee ,  Ji-Eun Lee ,  Kyoung-Ho Jung ,  Satoru Yamada ,  Moonyoung Jeong

IPC: H01L27/108 ,  H01L21/3215 ,  H01L29/49 ,  H01L21/28 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L27/10876 ,  H01L21/28088 ,  H01L21/3215 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: Provided are a semiconductor device having a gate and a method of forming the same. The method includes forming a gate dielectric, forming a first conductive material layer on the gate dielectric, forming a source material layer on the first conductive material layer, and diffusing a first element included in the source material layer into the first conductive material layer by performing a thermal treatment process to form a doped material layer.

公开(公告)号：US20130279275A1

公开(公告)日：2013-10-24

申请号：US13770150

申请日：2013-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyo-Suk Chae ,  Satoru Yamada

IPC: H01L29/78 ,  G11C7/00

CPC classification number: H01L29/7816 ,  G11C7/00 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/005

Abstract: A semiconductor memory device includes a bit line connected to a memory cell; an input/output line configured to input a data signal to the memory cell during a writing operation and to output a data signal stored in the memory cell during a reading operation; and a column select transistor including a first source/drain connected to the bit line and a second source/drain connected to the input/output line, wherein a resistance of the first source/drain is smaller than a resistance of the second source/drain.

Abstract translation: 半导体存储器件包括连接到存储器单元的位线; 输入/输出线，被配置为在写入操作期间将数据信号输入到存储器单元，并且在读取操作期间输出存储在存储单元中的数据信号; 以及列选择晶体管，其包括连接到所述位线的第一源极/漏极和连接到所述输入/输出线的第二源极/漏极，其中所述第一源极/漏极的电阻小于所述第二源极/漏极的电阻 。

公开(公告)号：US11844212B2

公开(公告)日：2023-12-12

申请号：US17748261

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H10B41/27 ,  H01L23/532 ,  G11C7/18 ,  G11C8/14 ,  H10B41/35 ,  G11C11/404 ,  G11C11/4097 ,  H01L49/02

CPC classification number: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L23/53295 ,  H01L28/60 ,  H10B41/35 ,  G11C11/404 ,  G11C11/4097

Abstract: A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

公开(公告)号：US11785761B2

公开(公告)日：2023-10-10

申请号：US17240486

申请日：2021-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Bong-Soo Kim ,  Junsoo Kim ,  Satoru Yamada ,  Wonsok Lee ,  Yoosang Hwang

IPC: H10B12/00 ,  H01L21/28 ,  H01L29/49 ,  H01L29/06

CPC classification number: H10B12/34 ,  H01L21/28088 ,  H01L29/0649 ,  H01L29/4966 ,  H10B12/053 ,  H10B12/315 ,  H10B12/488

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

公开(公告)号：US11735637B2

公开(公告)日：2023-08-22

申请号：US17400901

申请日：2021-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunae Cho ,  Dongjin Lee ,  Ji Eun Lee ,  Kyoung-Ho Jung ,  Dong Su Ko ,  Yongsu Kim ,  Jiho Yoo ,  Sung Heo ,  Hyun Park ,  Satoru Yamada ,  Moonyoung Jeong ,  Sungjin Kim ,  Gyeongsu Park ,  Han Jin Lim

IPC: H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/4236 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.