公开(公告)号：US11355349B2

公开(公告)日：2022-06-07

申请号：US17032356

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Park ,  Se Myeong Jang ,  Bong Soo Kim ,  Je Min Park

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/762

Abstract: A method includes forming hard mask patterns by depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate and etching the hard mask layer, forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask, oxidizing side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer, forming spacer patterns covering sides of the silicon oxide layer, forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns, etching the sacrificial layer and the silicon oxide layer, forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask, and forming activation pins by etching the substrate using the support mask patterns as an etch mask.

公开(公告)号：US20200035632A1

公开(公告)日：2020-01-30

申请号：US16351784

申请日：2019-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong Soo Kim

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/48 ,  H01L23/495 ,  H01L23/31

Abstract: A fan-out semiconductor package includes: a frame including first to third insulating layers, a first wiring layer disposed on a first surface of the first insulating layer and embedded in the second insulating layer, and a second wiring layer disposed on the third insulating layer, and having a through-hole penetrating through the first to third insulating layers; a semiconductor chip disposed in the through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface; an encapsulant covering at least portions of each of the frame and the semiconductor chip and filling at least portions of the through-hole; and a connection structure disposed on the frame and the active surface of the semiconductor chip and including redistribution layers electrically connected to the connection pads. The first and second wiring layers are electrically connected to the connection pads.

公开(公告)号：US10886246B2

公开(公告)日：2021-01-05

申请号：US16351784

申请日：2019-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong Soo Kim

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/48 ,  H01L23/31 ,  H01L23/495

Abstract: A fan-out semiconductor package includes: a frame including first to third insulating layers, a first wiring layer disposed on a first surface of the first insulating layer and embedded in the second insulating layer, and a second wiring layer disposed on the third insulating layer, and having a through-hole penetrating through the first to third insulating layers; a semiconductor chip disposed in the through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface; an encapsulant covering at least portions of each of the frame and the semiconductor chip and filling at least portions of the through-hole; and a connection structure disposed on the frame and the active surface of the semiconductor chip and including redistribution layers electrically connected to the connection pads. The first and second wiring layers are electrically connected to the connection pads.

公开(公告)号：US11901453B2

公开(公告)日：2024-02-13

申请号：US17587402

申请日：2022-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk Jang ,  Ki Hwan Kim ,  Su Jin Jung ,  Bong Soo Kim ,  Young Dae Cho

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/24

CPC classification number: H01L29/7848 ,  H01L21/02521 ,  H01L21/02603 ,  H01L21/02636 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

公开(公告)号：US11282833B2

公开(公告)日：2022-03-22

申请号：US16660976

申请日：2019-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Jin Lee ,  Ji Young Kim ,  Bong Soo Kim ,  Hyeon Kyun Noh ,  Moon Young Jeong

IPC: H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/22

Abstract: A semiconductor device is provided. The semiconductor device includes a first substrate, an active region defined by an isolation film in the first substrate, an oxide semiconductor layer on the first substrate in the active region, and not comprising silicon, a recess inside the oxide semiconductor layer, and a gate structure filling the recess, comprising a gate electrode and a capping film on the gate electrode, and having an upper surface on a same plane as an upper surface of the active region.

公开(公告)号：US11239363B2

公开(公告)日：2022-02-01

申请号：US16598012

申请日：2019-10-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk Jang ,  Ki Hwan Kim ,  Su Jin Jung ,  Bong Soo Kim ,  Young Dae Cho

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/24

Abstract: A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

公开(公告)号：US20200152462A1

公开(公告)日：2020-05-14

申请号：US16530286

申请日：2019-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min Park ,  Se Myeong Jang ,  Bong Soo Kim ,  Je Min Park

IPC: H01L21/033 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3213

Abstract: A method of forming a semiconductor device includes forming first sacrificial patterns on a lower structure, forming first remaining mask layers having a “U” shape between the first sacrificial patterns to be in contact with the first sacrificial patterns, forming first remaining mask patterns by pattering the first remaining mask layers, each of the first remaining mask patterns including a horizontal portion, parallel to an upper surface of the lower structure, and a vertical portion, perpendicular to the upper surface of the lower structure, forming second mask patterns spaced apart from the vertical portions of the first remaining mask patterns, removing the first sacrificial patterns remaining after forming the second mask patterns, and forming first mask patterns by etching the horizontal portions of the first remaining mask patterns.

公开(公告)号：US20190214293A1

公开(公告)日：2019-07-11

申请号：US16028794

申请日：2018-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu Jin Kim ,  Min Su Choi ,  Sung Hee Han ,  Bong Soo Kim ,  Yoo Sang Hwang

IPC: H01L21/762 ,  H01L27/108

CPC classification number: H01L21/76229 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a cell region and a peripheral region having different active region densities, forming cell trenches for limiting cell active regions in the cell region so that the cell active regions are formed to be spaced apart by a first width in a first direction and by a second width in a second direction, forming peripheral trenches for limiting a peripheral active region in the peripheral region, and forming, in the cell trenches, a first insulating layer continuously extending in the first and second directions and contacting sidewalls of the cell active regions, and having a thickness equal to or greater than half of the first width and less than half of the second width.

公开(公告)号：US10164017B2

公开(公告)日：2018-12-25

申请号：US15887773

申请日：2018-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuichiro Sasaki ,  Bong Soo Kim ,  Tae Gon Kim ,  Yoshiya Moriyama ,  Seung Hyun Song ,  Alexander Schmidt ,  Abraham Yoo ,  Heung Soon Lee ,  Kyung In Choi

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/223 ,  H01L21/265

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

公开(公告)号：US09911809B2

公开(公告)日：2018-03-06

申请号：US15424081

申请日：2017-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuichiro Sasaki ,  Bong Soo Kim ,  Tae Gon Kim ,  Yoshiya Moriyama ,  Seung Hyun Song ,  Alexander Schmidt ,  Abraham Yoo ,  Heung Soon Lee ,  Kyung In Choi

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L29/1083 ,  H01L21/2236 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.