公开(公告)号：US11604485B2

公开(公告)日：2023-03-14

申请号：US17665907

申请日：2022-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minshik Seok ,  Younghoon Lee ,  Kyungrae Kim ,  Kyungsoo Lee ,  Junho Huh

IPC: G05F1/56 ,  G06F1/26

Abstract: Multiple power management integrated circuits (PMICs) may perform communication and power sequence operation coordination between the multiple PMICs through a communication interface connected to two signal lines using a dual pin interface. The multiple PMICs include a main PMIC configured to communicate with at least one application processor through a system interface and at least one sub-PMIC configured to communicate with the main PMIC through the communication interface. A first signal line uses a single bidirectional signaling scheme, and a power status signal PSTATUS is exchanged between the main PMIC and the at least one sub-PMIC through the first signal line. A second signal line uses a single unidirectional signaling scheme, and a power sequence control signal PIF is transmitted from the main PMIC to the at least one sub-PMIC through the second signal line.

公开(公告)号：US12105661B2

公开(公告)日：2024-10-01

申请号：US17843245

申请日：2022-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minshik Seok ,  Siyoung Ok ,  Jaekyu Jang ,  Seungjae Lee ,  Younghoon Lee ,  Jeehye Lee ,  Sangjoo Jun

IPC: G06F13/42 ,  G06F1/30 ,  G06F9/4401

CPC classification number: G06F13/4208 ,  G06F1/30 ,  G06F9/4405

Abstract: An electronic device is provided. The electronic device includes a first power management integrated circuit (PMIC) with a first fault controller connected to a first node and a first interface circuit connected to a second node; a second PMIC with a second fault controller connected to the first node and a second interface circuit connected to the second node; and a third PMIC with a third fault controller connected to the first node and a third interface circuit connected to the second node. The first fault controller is configured to, during a power on sequence or a power off sequence, detect a change in a voltage level of the first node. The first interface circuit is configured to communicate with any one or any combination of the second interface circuit and communication and the third interface circuit based on the change in the voltage level of the first node.

公开(公告)号：US11275394B2

公开(公告)日：2022-03-15

申请号：US17027946

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minshik Seok ,  Younghoon Lee ,  Kyungrae Kim ,  Kyungsoo Lee ,  Junho Huh

IPC: G05F1/56 ,  G06F1/26

Abstract: Multiple power management integrated circuits (PMICs) may perform communication and power sequence operation coordination between the multiple PMICs through a communication interface connected to two signal lines using a dual pin interface. The multiple PMICs include a main PMIC configured to communicate with at least one application processor through a system interface and at least one sub-PMIC configured to communicate with the main PMIC through the communication interface. A first signal line uses a single bidirectional signaling scheme, and a power status signal PSTATUS is exchanged between the main PMIC and the at least one sub-PMIC through the first signal line. A second signal line uses a single unidirectional signaling scheme, and a power sequence control signal PIF is transmitted from the main PMIC to the at least one sub-PMIC through the second signal line.