公开(公告)号：US20160225635A1

公开(公告)日：2016-08-04

申请号：US14956609

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi-bong LEE ,  Wook-hyun KWON ,  Kyung-soo KIM ,  Seon-ah NAM ,  Yeon-ho PARK ,  Nak-jin SON

IPC: H01L21/308 ,  H01L29/66

CPC classification number: H01L21/3086 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of active fins over a semiconductor substrate, sequentially forming first and second hard mask layers over the active fins, forming a first hard mask pattern by etching the second hard mask layer, trimming the first hard mask pattern to form a trimmed hard mask pattern, forming a first photo resist pattern over the first hard mask layer, forming second hard mask patterns by etching the first hard mask layer by using the trimmed hard mask pattern and the first photo resist pattern as an etching mask, and forming active fin patterns by etching the active fins by using the second hard mask patterns as an etching mask.

Abstract translation: 一种制造半导体器件的方法包括在半导体衬底上形成多个活性鳍片，在活性鳍片上依次形成第一和第二硬掩模层，通过蚀刻第二硬掩模层形成第一硬掩模图案，修剪第一硬质掩模层 掩模图案以形成修剪的硬掩模图案，在第一硬掩模层上形成第一光刻胶图案，通过使用修剪的硬掩模图案和第一光致抗蚀剂图案作为第一硬掩模图案来蚀刻第一硬掩模层而形成第二硬掩模图案 蚀刻掩模，并且通过使用第二硬掩模图案作为蚀刻掩模蚀刻活性散热片来形成活性鳍图案。

公开(公告)号：US20140252440A1

公开(公告)日：2014-09-11

申请号：US14175305

申请日：2014-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min PARK ,  Dae-ik KIM ,  Ji-young KIM ,  Nak-jin SON ,  Yoo-sang HWANG

IPC: H01L23/48 ,  H01L27/105

CPC classification number: H01L23/485 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/41791 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at least an insulating layer, and a conductive plug structure electrically connecting the conductive line to the target connection region, wherein the conductive plug includes a first conductive plug having a first side wall, a bottom surface contacting the target connection region of the substrate, and a second side wall facing the first side wall of the conductive line, and a second conductive plug between the conductive line and the first conductive plug. The second conductive plug contacts both the first side wall of the conductive line and the second side wall of the first conductive plug.

Abstract translation: 半导体器件包括具有目标连接区域的衬底; 导电线，其具有通过至少绝缘层与衬底间隔开的第一侧壁和将导电线电连接到目标连接区域的导电插塞结构，其中导电插塞包括第一导电插塞，第一导电插塞具有第一侧壁 ，与基板的目标连接区域接触的底表面和面对导电线的第一侧壁的第二侧壁，以及在导线和第一导电塞之间的第二导电塞。 第二导电插头接触导电线的第一侧壁和第一导电插塞的第二侧壁。