公开(公告)号：US20250142906A1

公开(公告)日：2025-05-01

申请号：US18655387

申请日：2024-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGUK JANG ,  JINBUM KIM ,  ILYOUNG YOON

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a barrier rib separating the source/drain region into a plurality of parts. A first part of the plurality of parts of the source/drain region includes a first epitaxial layer having a lower end disposed on the active pattern and a sidewall part extending from the lower end in a third direction crossing first and second directions and connected to the channel pattern. A second epitaxial layer is disposed on the first epitaxial layer and has a composition different from a composition of the first epitaxial layer. In a cross-section cut from the center of the source/drain region in the first direction to the second and third directions, a lower end of the first epitaxial layer of the first part of the plurality of parts of the source/drain region has an asymmetric shape around an axis extending in the third direction.

公开(公告)号：US20240413086A1

公开(公告)日：2024-12-12

申请号：US18387997

申请日：2023-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINBUM KIM ,  GUIFU YANG ,  Suk Yang ,  SANGMOON LEE ,  SUNGUK JANG ,  SUNG-HWAN JANG ,  Wonhee Choi

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Provided is a semiconductor device including a lower pattern layer including a first semiconductor material; a first conductivity-type doped pattern layer disposed on the lower pattern layer and including a semiconductor material doped with a first conductivity-type impurity; a source/drain pattern disposed on the first conductivity-type doped pattern layer and including a semiconductor material doped with a second conductivity-type impurity different from the first conductivity-type impurity; a channel pattern including semiconductor patterns connected between the source/drain patterns, stacked apart from each other, and including a second semiconductor material different from the first semiconductor material; and a gate pattern disposed on the first conductivity-type doped pattern layer and between the source/drain patterns, and surrounding the channel pattern.