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    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND RELATED METHOD OF MANUFACTURE
    1.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND RELATED METHOD OF MANUFACTURE 审中-公开
    三维半导体存储器件及其制造方法

    公开(公告)号：US20150262826A1

    公开(公告)日：2015-09-17

    申请号：US14726648

    申请日：2015-06-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JONG IN YUN ,  JIN-SOO LIM ,  HANSOO KIM ,  SUNG-HWAN JANG ,  YOUNGWOO PARK ,  BYOUNGKEUN SON

    IPC: H01L21/28 ,  H01L21/311 ,  H01L27/115

    CPC classification number: H01L29/78 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    Abstract: A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second material layers on a substrate, forming a penetration dent penetrating the thin layer structure and exposing a top surface of the substrate recessed by the penetration dent, forming a vertical insulation layer penetrating the thin layer structure to cover an inner wall of the penetration dent, forming a semiconductor pattern penetrating the vertical insulation layer at the penetration dent to be inserted into the substrate, and forming an oxide layer between the thin layer structure and the substrate by oxidizing a sidewall of the penetration dent.

    Abstract translation: 一种制造三维半导体存储器件的方法包括通过在衬底上交替地堆叠第一和第二材料层来形成薄层结构，形成穿透薄层结构的穿透凹陷，并使基底凹陷的顶部表面露出 形成穿透薄层结构的垂直绝缘层以覆盖穿透凹陷的内壁，形成穿透穿孔凹陷处的垂直绝缘层的半导体图案，以插入到基板中，并且在薄的层间形成氧化物层 通过氧化渗透凹陷的侧壁来形成层状结构和基底。

    MEMORY DEVICE INCLUDING BITLINE SENSE AMPLIFIER AND OPERATING METHOD THEREOF
    2.
    发明申请
    MEMORY DEVICE INCLUDING BITLINE SENSE AMPLIFIER AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20220020423A1

    公开(公告)日：2022-01-20

    申请号：US17202466

    申请日：2021-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JONG-HO MOON ,  SUNG-HWAN JANG

    IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4096

    Abstract: Disclosed are a memory device and an operating method thereof. The memory device includes a bitline sense amplifier connected to a bitline and a complementary bitline connected to a memory cell, and a sense amplifier driver circuit. The bitline sense amplifier senses and amplifies a voltage difference by developing a voltage of the bitline and a voltage of the complementary bitline. The sense amplifier driver circuit includes a pull-up circuit adjusting a level of a bitline low-level voltage developed by the bitline sense amplifier to be higher than a ground voltage in response to a first pull-up pulse, and a pull-down circuit adjusting the level of the bitline low level adjusted by the pull-up circuit to be equal to the ground voltage in response to a pull-down pulse. A pulse generator generates the first pull-up pulse and the pull-down pulse based on a command received from a host.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240413086A1

    公开(公告)日：2024-12-12

    申请号：US18387997

    申请日：2023-11-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JINBUM KIM ,  GUIFU YANG ,  Suk Yang ,  SANGMOON LEE ,  SUNGUK JANG ,  SUNG-HWAN JANG ,  Wonhee Choi

    IPC: H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

    Abstract: Provided is a semiconductor device including a lower pattern layer including a first semiconductor material; a first conductivity-type doped pattern layer disposed on the lower pattern layer and including a semiconductor material doped with a first conductivity-type impurity; a source/drain pattern disposed on the first conductivity-type doped pattern layer and including a semiconductor material doped with a second conductivity-type impurity different from the first conductivity-type impurity; a channel pattern including semiconductor patterns connected between the source/drain patterns, stacked apart from each other, and including a second semiconductor material different from the first semiconductor material; and a gate pattern disposed on the first conductivity-type doped pattern layer and between the source/drain patterns, and surrounding the channel pattern.

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