公开(公告)号：US20200219879A1

公开(公告)日：2020-07-09

申请号：US16439999

申请日：2019-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Cheol SHIN ,  Myung Gil KANG ,  Sadaaki MASUOKA ,  Sang Hoo LEE ,  Sung Man WHANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L21/8238 ,  H01L21/02

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

公开(公告)号：US20240096894A1

公开(公告)日：2024-03-21

申请号：US18521253

申请日：2023-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Cheol SHIN ,  Myung Gil KANG ,  Sadaaki MASUOKA ,  Sang Hoon LEE ,  Sung Man WHANG

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

公开(公告)号：US20130252393A1

公开(公告)日：2013-09-26

申请号：US13687104

申请日：2012-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keon-Yong CHEON ,  Dong-Won KIM ,  Sung-Man LIM ,  Sadaaki MASUOKA ,  Yaoqi DONG

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: In a method of forming MOS transistor, a gate structure is formed on a substrate and a first spacer layer is formed on the substrate conformal to the gate structure. A second spacer layer is formed on the first spacer layer. A second spacer is formed on the first spacer layer corresponding to a sidewall of the gate structure by partially removing the second spacer layer from the first spacer layer. Impurities are implanted in the substrate by an ion implantation process using the gate structure including the first spacer layer and the second spacer as an ion implantation mask to form source/drain extension regions at surface portions of the substrate around the gate structure.

Abstract translation: 在形成MOS晶体管的方法中，在衬底上形成栅极结构，并且在与栅极结构一致的衬底上形成第一间隔层。 在第一间隔层上形成第二间隔层。 通过从第一间隔层部分去除第二间隔层，在对应于栅极结构的侧壁的第一间隔层上形成第二间隔物。 通过使用包括第一间隔层和第二间隔物的栅极结构作为离子注入掩模的离子注入工艺将杂质注入到衬底中，以在栅极结构周围的衬底的表面部分处形成源极/漏极延伸区域。

公开(公告)号：US20220406779A1

公开(公告)日：2022-12-22

申请号：US17894427

申请日：2022-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Cheol SHIN ,  Myung Gil KANG ,  Sadaaki MASUOKA ,  Sang Hoon LEE ,  Sung Man WHANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02 ,  H01L29/16 ,  H01L21/8238

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

公开(公告)号：US20210020638A1

公开(公告)日：2021-01-21

申请号：US17030841

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Cheol SHIN ,  Myung Gil KANG ,  Sadaaki MASUOKA ,  Sang Hoon LEE ,  Sung Man WHANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02 ,  H01L29/16 ,  H01L21/8238

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.