公开(公告)号：US20240096894A1

公开(公告)日：2024-03-21

申请号：US18521253

申请日：2023-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Cheol SHIN ,  Myung Gil KANG ,  Sadaaki MASUOKA ,  Sang Hoon LEE ,  Sung Man WHANG

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

公开(公告)号：US20210013324A1

公开(公告)日：2021-01-14

申请号：US17038004

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Jin Bum KIM ,  MunHyeon KIM ,  Hyoung Sub KIM ,  Tae Jin PARK ,  Kwan Heum LEE ,  Chang Woo NOH ,  Maria TOLEDANO LU QUE ,  Hong Bae PARK ,  Si Hyung LEE ,  Sung Man WHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

公开(公告)号：US20200219879A1

公开(公告)日：2020-07-09

申请号：US16439999

申请日：2019-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Cheol SHIN ,  Myung Gil KANG ,  Sadaaki MASUOKA ,  Sang Hoo LEE ,  Sung Man WHANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L21/8238 ,  H01L21/02

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

公开(公告)号：US20220406779A1

公开(公告)日：2022-12-22

申请号：US17894427

申请日：2022-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Cheol SHIN ,  Myung Gil KANG ,  Sadaaki MASUOKA ,  Sang Hoon LEE ,  Sung Man WHANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02 ,  H01L29/16 ,  H01L21/8238

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

公开(公告)号：US20210020638A1

公开(公告)日：2021-01-21

申请号：US17030841

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Cheol SHIN ,  Myung Gil KANG ,  Sadaaki MASUOKA ,  Sang Hoon LEE ,  Sung Man WHANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02 ,  H01L29/16 ,  H01L21/8238

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

公开(公告)号：US20190198639A1

公开(公告)日：2019-06-27

申请号：US16037922

申请日：2018-07-17

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Jin Bum KIM ,  MunHyeon KIM ,  Hyoung Sub KIM ,  Tae Jin PARK ,  Kwan Heum LEE ,  Chang Woo NOH ,  Maria TOLEDANO LU QUE ,  Hong Bae PARK ,  Si Hyung LEE ,  Sung Man WHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

公开(公告)号：US20170345897A1

公开(公告)日：2017-11-30

申请号：US15256136

申请日：2016-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Gil KANG ,  Seung Han PARK ,  Yong Hee PARK ,  Sang Hoon BAEK ,  Sang Woo LEE ,  Keon Yong CHEON ,  Sung Man WHANG

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/41741 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/7827 ,  H01L29/7851

Abstract: A vertical field effect transistor is provided as follows. A substrate has a lower drain and a lower source arranged along a first direction in parallel to an upper surface of the substrate. A fin structure is disposed on the substrate and extended vertically from the upper surface of the substrate. The fin structure includes a first end portion and a second end portion arranged along the first direction. A bottom surface of a first end portion of the fin structure and a bottom surface of a second end portion of the fin structure overlap the lower drain and the lower source, respectively. The fin structure includes a sidewall having a lower sidewall region, a center sidewall region and an upper sidewall region. A gate electrode surrounds the center side sidewall region of the fin structure.