公开(公告)号：US20240405104A1

公开(公告)日：2024-12-05

申请号：US18648580

申请日：2024-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Gwon KIM ,  Myung Gil KANG ,  Jin Kyu KIM ,  Dong Won KIM ,  Beom Jin PARK

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

Abstract: A semiconductor device is provided. The semiconductor includes at least one of a well area in a substrate and having a first conductivity-type; impurity-implanted areas in the well, and having a second conductivity-type different from the first conductivity-type and arranged in a first direction, a first fin structure on the impurity-implanted area and having the second conductivity-type, wherein the first fin structure includes first semiconductor patterns and first sacrificial patterns alternately stacked; a first contact on the first fin structure; a first epitaxial pattern on the well area and having the first conductivity-type; and a second contact on the first epitaxial pattern.

公开(公告)号：US20240332378A1

公开(公告)日：2024-10-03

申请号：US18463488

申请日：2023-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younggwon KIM ,  Seung Geun JUNG ,  Myung Gil KANG ,  Gyeom KIM ,  Dongwon KIM

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/41733 ,  H01L21/76805 ,  H01L23/5226 ,  H01L29/0847 ,  H01L29/401 ,  H01L23/53295 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate, a lower pattern on the substrate, a channel pattern on the lower pattern, a source/drain pattern on both sides of the channel pattern, a gate structure surrounding the channel pattern, a contact electrode electrically connected to the source/drain pattern, an etch stop layer between the gate structure and the contact electrode, and a contact interface layer on the source/drain pattern. The contact interface layer may include a first region between the source/drain pattern and the contact electrode and a second region between the source/drain pattern and the etch stop layer.

公开(公告)号：US20240222374A1

公开(公告)日：2024-07-04

申请号：US18457313

申请日：2023-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Gwon KIM ,  Myung Gil KANG ,  Soo Jin JEONG ,  Dong Won KIM ,  Beom Jin PARK ,  Hong Seon YANG

IPC: H01L27/092 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes a substrate that includes a first region and a second region, a first active pattern on the first region, a first gate structure that intersects the first active pattern, a first epitaxial pattern connected to the first active pattern and includes n-type impurities, a first source/drain contact that penetrates an upper surface of the first epitaxial pattern and is connected to the first epitaxial pattern, a second active pattern on the second region, a second gate structure that intersects the second active pattern, a second epitaxial pattern connected to the second active pattern and includes p-type impurities, and a second source/drain contact that penetrates an upper surface of the second epitaxial pattern and is connected to the second epitaxial pattern. A lower surface of the first source/drain contact is lower than a lower surface of the second source/drain contact.

公开(公告)号：US20220085161A1

公开(公告)日：2022-03-17

申请号：US17229045

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo NOH ,  Myung Gil KANG ,  Tae Young KIM ,  Geum Jong BAE ,  Keun Hwi CHO

IPC: H01L29/06

Abstract: A semiconductor device includes a substrate, first to sixth nanowires extending in a first direction and spaced apart from each other, first to third gate electrodes extending in a second direction and respectively on first to third regions of the substrate, a first interface layer of a first thickness between the first gate electrode and the second nanowire, a second interface layer of a second thickness between the third gate electrode and the sixth nanowire. The first to third gate electrodes respectively may surround the first and second nanowires, third and fourth nanowires, and fifth and sixth nanowires. A first internal spacer may be on a side wall of at least one of the first to third gate electrodes. In the first direction, a first length of the first nanowire may be smaller than a second length of the third nanowire.

公开(公告)号：US20170365526A1

公开(公告)日：2017-12-21

申请号：US15290456

申请日：2016-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo Yeon JEONG ,  Myung Gil KANG

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/49 ,  H01L29/06 ,  H01L27/092 ,  H01L23/535 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L21/823821 ,  H01L21/823828 ,  H01L21/823885 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785

Abstract: A vertical fin field effect transistor (V-FinFET) is provided as follows. A substrate has a lower source/drain (S/D). A fin structure extends vertically from an upper surface of the lower S/D. The fin structure includes a sidewall having an upper sidewall portion, a lower sidewall portion and a center sidewall portion positioned therebetween. An upper S/D is disposed on an upper surface of the fin structure. An upper spacer is disposed on the upper sidewall portion. A lower spacer is disposed on the lower sidewall portion. A stacked structure including a gate oxide layer and a first gate electrode is disposed on an upper surface of the lower spacer, the center sidewall portion and a lower surface of the upper spacer. A second gate electrode is disposed on the first gate electrode

公开(公告)号：US20220328496A1

公开(公告)日：2022-10-13

申请号：US17541790

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil KANG ,  Seunghun LEE ,  Sangdeok KWON ,  Keun Hwi CHO ,  Sung Gi HUR

IPC: H01L27/11 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the pair of first source/drain patterns, wherein the first channel pattern includes a plurality of semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode on the first channel pattern, a first gate cutting pattern that is adjacent to the first channel pattern and penetrates the first gate electrode, and a first residual pattern between the first gate cutting pattern and the first channel pattern. The first residual pattern covers an outermost sidewall of at least one semiconductor pattern of the plurality of semiconductor patterns of the first channel pattern. The first gate electrode includes, on an upper portion of the first gate electrode, a first extension that vertically overlaps the first residual pattern.

公开(公告)号：US20220109057A1

公开(公告)日：2022-04-07

申请号：US17245601

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon KIM ,  Myung Gil KANG ,  Wandon KIM

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/40

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The device may include a substrate, an active pattern in an upper portion of the substrate and is extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction, a first gate spacer covering a side surface of the gate electrode, a first inhibition layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be between the gate oxide layer and the gate electrode.

公开(公告)号：US20190198669A1

公开(公告)日：2019-06-27

申请号：US16128995

申请日：2018-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Hee PARK ,  Myung Gil KANG ,  Young-Seok SONG ,  Keon Yong CHEON

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/1037

Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.

公开(公告)号：US20190198648A1

公开(公告)日：2019-06-27

申请号：US16151511

申请日：2018-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil KANG ,  Ill Seo KANG ,  Yong Hee PARK ,  Sang Hoon BAEK ,  Keon Yong CHEON

IPC: H01L29/732 ,  H01L27/082 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/51 ,  H01L21/308 ,  H01L21/28

Abstract: A vertical bipolar transistor including a substrate including a first well of a first conductivity type and a second well of a second conductivity type different from the first conductivity type, the first well adjoining the second well, a first fin extending, from the first well, a second fin extending from the first well, a third fin extending from the second well, a first conductive region on the first fin, having the second conductivity type and configured to serve as an emitter of the vertical bipolar transistor, a second conductive region on the second fin, having the first conductivity type, and configured to serve as a base of the vertical bipolar transistor, and a third conductive region on the third fin, having the second conductivity type, and configured to serve as a collector of the vertical bipolar transistor may be provided.

公开(公告)号：US20230299139A1

公开(公告)日：2023-09-21

申请号：US18057986

申请日：2022-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi CHO ,  Myung Gil KANG ,  Gibum KIM ,  Dongwon KIM

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66439

Abstract: A semiconductor device includes an active region on a substrate, source/drain patterns on the active region, channel patterns on the active region and connected to the source/drain patterns, each of the channel patterns including a plurality of semiconductor patterns, which are vertically stacked to be spaced apart from each other, gate electrodes, which are respectively on the channel patterns and are extended in a first direction and parallel to each other, and active contacts, which are electrically and respectively connected to the source/drain patterns. A bottom surface of a first active contact is located at a first level, and a bottom surface of a second active contact is located at a second level higher than the first level. A bottom surface of a third active contact is located at a third level higher than the second level.