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公开(公告)号:US20180323754A1
公开(公告)日:2018-11-08
申请号:US15862213
申请日:2018-01-04
Inventor: Jihoon KIM , Bumman KIM , Kyunghoon MOON , Seokwon LEE , Daechul JEONG , Byungjoon PARK , Juho SON
Abstract: The method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The method includes intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The system includes a power amplification device capable of minimizing the effect of envelope impedance. The power amplification device may be incorporated in a terminal and a base station.
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公开(公告)号:US20250062264A1
公开(公告)日:2025-02-20
申请号:US18623202
申请日:2024-04-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jihyun LEE , Kang Joon LEE , Seokwon LEE
IPC: H01L23/00 , H01L23/498 , H01L23/60
Abstract: A semiconductor package including a first structure, a second structure, and an interconnect structure between the first structure and the second structure. The interconnect structure includes a first region extending from a center of the interconnect structure to a first distance, and a second region outside the first region. The interconnect structure includes a plurality of first connection members in the first region and a plurality of second connection members in the second region. The plurality of first connection members are arranged in a staggered form, and the plurality of second connection members are arranged in rows.
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公开(公告)号:US20240071895A1
公开(公告)日:2024-02-29
申请号:US18353279
申请日:2023-07-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seoeun KYUNG , Byung Ho KIM , Youngbae KIM , Hongwon KIM , Seokwon LEE , Jae-Ean LEE , Dahee KIM
IPC: H01L23/498 , H01L23/00 , H01L23/538 , H01L25/10 , H01L25/18
CPC classification number: H01L23/49838 , H01L23/5386 , H01L24/16 , H01L25/105 , H01L25/18 , H01L23/3128 , H01L23/49822 , H01L23/5385 , H01L24/48 , H01L2224/16227 , H01L2224/48091 , H01L2224/48105 , H01L2224/48227 , H01L2225/1035 , H01L2225/1058
Abstract: A semiconductor package may include a lower redistribution layer including a lower wiring and a lower via, an embedded region on the lower redistribution layer, a core layer on the lower redistribution layer and including a core via, and an under bump structure including an under bump pad on a lower surface of the lower redistribution layer and an under bump via connecting the lower wiring and the under bump pad, the under bump pad may overlap the under bump via, the lower via, and the core via in a plan view, and the under bump via may be spaced apart from at least one of the lower via and the core via in the plan view.
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