公开(公告)号：US20250096135A1

公开(公告)日：2025-03-20

申请号：US18962181

申请日：2024-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun LEE ,  Seokjung YUN ,  Chang-Sup LEE ,  Seong Soon CHO ,  Jeehoon HAN

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US20200243445A1

公开(公告)日：2020-07-30

申请号：US16850391

申请日：2020-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Jung YUN ,  Sung-Hun LEE ,  Jee-Hoon HAN ,  Yong-Won CHUNG ,  Seong Soon CHO

IPC: H01L23/528 ,  H01L27/11575 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582

Abstract: Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n-1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n-1)-th extended gate lines serves as a pad region, and the pad regions have different areas.