公开(公告)号：US20200243445A1

公开(公告)日：2020-07-30

申请号：US16850391

申请日：2020-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Jung YUN ,  Sung-Hun LEE ,  Jee-Hoon HAN ,  Yong-Won CHUNG ,  Seong Soon CHO

IPC: H01L23/528 ,  H01L27/11575 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582

Abstract: Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n-1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n-1)-th extended gate lines serves as a pad region, and the pad regions have different areas.

公开(公告)号：US20200075101A1

公开(公告)日：2020-03-05

申请号：US16659715

申请日：2019-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Da Woon JEONG ,  Sung-Hun LEE ,  Seokjung YUN ,  Hyunmog PARK ,  JoongShik SHIN ,  Young-Bae YOON

IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H01L49/02

Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

公开(公告)号：US20250096135A1

公开(公告)日：2025-03-20

申请号：US18962181

申请日：2024-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun LEE ,  Seokjung YUN ,  Chang-Sup LEE ,  Seong Soon CHO ,  Jeehoon HAN

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US20220367511A1

公开(公告)日：2022-11-17

申请号：US17729549

申请日：2022-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younjeong HWANG ,  Minbum KIM ,  Hojun SEONG ,  Sung-Hun LEE ,  Juneon JIN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528

Abstract: A three-dimensional semiconductor memory device may include a source structure on a substrate, a stack structure including electrode layers and inter-electrode insulating layers, which are on the source structure and are alternately stacked, a vertical structure penetrating the stack structure and the source structure and being adjacent to the substrate, and a separation insulation pattern penetrating the stack structure and the source structure and being spaced apart from the vertical structure. The uppermost one of the inter-electrode insulating layers may include a first impurity injection region located at a first height from a top surface of the substrate. The stack structure may define a groove, in which the separation insulation pattern is located. An inner sidewall of the groove may define a recess region, which is located at the first height from the top surface of the substrate and is recessed toward the vertical structure.

公开(公告)号：US20150325580A1

公开(公告)日：2015-11-12

申请号：US14746205

申请日：2015-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Hun LEE ,  Ki-Yong KIM ,  Sung-Wook PARK ,  Gyu-Yeol LEE

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/823437 ,  H01L21/823443 ,  H01L21/823456 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/788

Abstract: In a semiconductor device, a first gate structure is provided in a cell transistor region and includes a floating gate electrode, a first dielectric layer pattern, and a control gate electrode including a first metal silicide pattern. A second gate structure is provided in a selecting transistor region and includes a first conductive layer pattern, a second dielectric layer pattern, and a first gate electrode including a second metal silicide pattern. A third gate structure is provided in a peripheral circuit region and includes a second conductive layer pattern, a third dielectric layer pattern including opening portions on the second conductive layer pattern, and a second gate electrode including a concavo-convex portion at an upper surface portion thereof and a third metal silicide pattern. The third metal silicide pattern has a uniform thickness.

Abstract translation: 在半导体器件中，第一栅极结构设置在单元晶体管区域中，并且包括浮置栅电极，第一介电层图案和包括第一金属硅化物图案的控制栅电极。 第二栅极结构设置在选择晶体管区域中，并且包括第一导电层图案，第二介电层图案和包括第二金属硅化物图案的第一栅电极。 第三栅极结构设置在外围电路区域中，并且包括第二导电层图案，在第二导电层图案上包括开口部分的第三介电层图案，以及在上表面部分包括凹凸部分的第二栅电极 和第三金属硅化物图案。 第三金属硅化物图案具有均匀的厚度。