公开(公告)号：US20230420349A1

公开(公告)日：2023-12-28

申请号：US18125409

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Narae Shin ,  Seongho Shin ,  Seonghwan Jeon

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/4985 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16227 ,  H01L23/3107

Abstract: A semiconductor package includes a base film, a first conductive structure disposed on a first surface of the base film, a second conductive structure disposed on a second surface of the base film, a via passing through the base film and connecting the first conductive structure to the second conductive structure, a semiconductor chip on the first surface and electrically connected to the first conductive structure, a first insulating layer covering the first conductive structure and including a first opening exposing a first conductive pattern of the first conductive structure, a first conductive layer disposed on the first insulating layer, covering the first insulating layer and the semiconductor chip, and contacting a region of the first conductive pattern exposed by the first opening, and a second conductive layer disposed on the second surface, covering the second conductive structure, and contacting at least a portion of the second conductive structure.

公开(公告)号：US11631660B2

公开(公告)日：2023-04-18

申请号：US17243127

申请日：2021-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho Lee ,  Eunseok Song ,  Kyungsuk Oh ,  Seonghwan Jeon

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

公开(公告)号：US12211829B2

公开(公告)日：2025-01-28

申请号：US18121664

申请日：2023-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho Lee ,  Eunseok Song ,  Kyungsuk Oh ,  Seonghwan Jeon

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/495 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

公开(公告)号：US20230223390A1

公开(公告)日：2023-07-13

申请号：US18121664

申请日：2023-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho Lee ,  Eunseok Song ,  Kyungsuk Oh ,  Seonghwan Jeon

IPC: H10B80/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L23/495

CPC classification number: H10B80/00 ,  H01L24/48 ,  H01L23/3128 ,  H01L24/16 ,  H01L23/481 ,  H01L24/73 ,  H01L23/5383 ,  H01L23/4952 ,  H01L2224/48145 ,  H01L2224/16227 ,  H01L2224/73257

Abstract: A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

公开(公告)号：US20220059519A1

公开(公告)日：2022-02-24

申请号：US17243127

申请日：2021-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho Lee ,  Eunseok Song ,  Kyungsuk Oh ,  Seonghwan Jeon

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.