公开(公告)号：US11631660B2

公开(公告)日：2023-04-18

申请号：US17243127

申请日：2021-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho Lee ,  Eunseok Song ,  Kyungsuk Oh ,  Seonghwan Jeon

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

公开(公告)号：US11984421B2

公开(公告)日：2024-05-14

申请号：US17228111

申请日：2021-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok Song ,  Hongjoo Baek ,  Kyungsuk Oh ,  Manho Lee ,  Hyuekjae Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L24/24 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/5286 ,  H01L2224/24265 ,  H01L2924/19041

Abstract: An integrated circuit chip includes a substrate having an active surface and a back surface opposite to the active surface; a front-end-of-line (FEOL) structure disposed on the active surface of the substrate; a first back-end-of-line (BEOL) structure disposed on the FEOL structure; an intermediate connection layer disposed under the back surface of the substrate, the intermediate connection layer including a charge storage, and metal posts disposed around the charge storage; and a re-distribution structure layer disposed under the intermediate connection layer.

公开(公告)号：US11862618B2

公开(公告)日：2024-01-02

申请号：US17369228

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho Lee ,  Eunseok Song ,  Keung Beum Kim ,  Kyung Suk Oh ,  Eon Soo Jang

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L27/01 ,  H01L49/02

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/08 ,  H01L24/16 ,  H01L27/016 ,  H01L28/90 ,  H01L2224/08147 ,  H01L2224/16147

Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

公开(公告)号：US20220139863A1

公开(公告)日：2022-05-05

申请号：US17228111

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunseok Song ,  Hongjoo Baek ,  Kyungsuk Oh ,  Manho Lee ,  Hyuekjae Lee

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/48 ,  H01L23/31

Abstract: An integrated circuit chip includes a substrate having an active surface and a back surface opposite to the active surface; a front-end-of-line (FEOL) structure disposed on the active surface of the substrate; a first back-end-of-line (BEOL) structure disposed on the FEOL structure; an intermediate connection layer disposed under the back surface of the substrate, the intermediate connection layer including a charge storage, and metal posts disposed around the charge storage; and a re-distribution structure layer disposed under the intermediate connection layer.

公开(公告)号：US12211829B2

公开(公告)日：2025-01-28

申请号：US18121664

申请日：2023-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho Lee ,  Eunseok Song ,  Kyungsuk Oh ,  Seonghwan Jeon

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/495 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

公开(公告)号：US20230223390A1

公开(公告)日：2023-07-13

申请号：US18121664

申请日：2023-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho Lee ,  Eunseok Song ,  Kyungsuk Oh ,  Seonghwan Jeon

IPC: H10B80/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L23/495

CPC classification number: H10B80/00 ,  H01L24/48 ,  H01L23/3128 ,  H01L24/16 ,  H01L23/481 ,  H01L24/73 ,  H01L23/5383 ,  H01L23/4952 ,  H01L2224/48145 ,  H01L2224/16227 ,  H01L2224/73257

Abstract: A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

公开(公告)号：US20220059519A1

公开(公告)日：2022-02-24

申请号：US17243127

申请日：2021-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho Lee ,  Eunseok Song ,  Kyungsuk Oh ,  Seonghwan Jeon

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

公开(公告)号：US20240284683A1

公开(公告)日：2024-08-22

申请号：US18244429

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Seo ,  Manho Lee ,  Sukkang Sung ,  Cheonan Lee

IPC: H10B80/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06582

Abstract: A nonvolatile memory package includes first nonvolatile memory devices configured to be stacked, second nonvolatile memory devices configured to be stacked, and an interface chip connected to an external device through a bonding channel, connected to one of the first nonvolatile memory devices through a first bonding channel, and connected to one of the second nonvolatile memory devices through a second bonding channel, wherein the interface chip includes input/output pads connected to the bonding channel, first input/output pads connected to the first bonding channel, and second input/output pads connected to the second bonding channel, and wherein, for cross-channel shielding, the first input/output pads and the second input/output pads are alternately arranged for each channel.

公开(公告)号：US12057441B2

公开(公告)日：2024-08-06

申请号：US17648549

申请日：2022-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Manho Lee ,  Eunseok Song ,  Kyungsuk Oh

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/17 ,  H01L24/24 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/171 ,  H01L2224/24145 ,  H01L2224/73259 ,  H01L2924/13067

Abstract: A semiconductor package includes a lower redistribution layer, a lower semiconductor chip and a plurality of conductive connection structures attached to the lower redistribution layer. An upper redistribution layer is disposed on the lower semiconductor chip and the plurality of conductive connection structures. An upper semiconductor chip has an active plane corresponding to an active plane of the lower semiconductor chip and is disposed on the upper redistribution layer. The lower semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first substrate. An upper wiring structure is disposed on the first surface of the semiconductor substrate. A buried power rail fills a portion of a buried rail hole extending from the first surface toward the second surface. A through electrode fills a through hole extending from the second surface toward the first surface.

公开(公告)号：US20220352128A1

公开(公告)日：2022-11-03

申请号：US17648549

申请日：2022-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Manho Lee ,  Eunseok Song ,  Kyungsuk Oh

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/48

Abstract: A semiconductor package includes a lower redistribution layer, a lower semiconductor chip and a plurality of conductive connection structures attached to the lower redistribution layer. An upper redistribution layer is disposed on the lower semiconductor chip and the plurality of conductive connection structures. An upper semiconductor chip has an active plane corresponding to an active plane of the lower semiconductor chip and is disposed on the upper redistribution layer. The lower semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first substrate. An upper wiring structure is disposed on the first surface of the semiconductor substrate. A buried power rail fills a portion of a buried rail hole extending from the first surface toward the second surface. A through electrode fills a through hole extending from the second surface toward the first surface.