公开(公告)号：US20210065803A1

公开(公告)日：2021-03-04

申请号：US16834025

申请日：2020-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junha LEE ,  Seonkyoo LEE ,  Jeongdon IHM ,  Byunghoon JEONG

IPC: G11C16/06 ,  H01L25/065 ,  H01L23/66 ,  H01L25/18

Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.

公开(公告)号：US20240212729A1

公开(公告)日：2024-06-27

申请号：US18392199

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung KIM ,  Seonkyoo LEE ,  Seungjun BAE ,  Taesung LEE

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1066

Abstract: A storage device includes a first chip and a second chip configured to exchange data with the first chip. The first chip may transmit a data strobe signal and a plurality of data signals, applied with different delay times, to the second chip. The second chip may sample the plurality of data signals, applied with the different delay times, using the data strobe signal received from the first chip during data training.

公开(公告)号：US20250103091A1

公开(公告)日：2025-03-27

申请号：US18756305

申请日：2024-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tongsung KIM ,  Woojung KIM ,  Yoonji PARK ,  Younghoon SON ,  Seonkyoo LEE ,  Ilyoung JIN

IPC: G06F1/08 ,  G06F1/10

Abstract: Provided are an apparatus and a method for adjusting a skew between data and a clock. The apparatus driven by a supply voltage includes a clock circuit that adjusts a skew between data and a clock. The clock circuit performs a first loop operation through a first loop and a second loop operation through a second loop, based on a phase difference between data and a clock. The first loop operation is performed until there is no phase difference between the data and the clock, and the second loop operation is performed until a first slope representing a change in delay of the data with respect to the levels of the power voltage and a second slope representing a change in delay of the clock become identical to each other.

公开(公告)号：US20220229599A1

公开(公告)日：2022-07-21

申请号：US17528285

申请日：2021-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin JO ,  Tongsung KIM ,  Chiweon YOON ,  Seonkyoo LEE ,  Byunghoon JEONG

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H03K19/00

Abstract: A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.

公开(公告)号：US20210366546A1

公开(公告)日：2021-11-25

申请号：US17393784

申请日：2021-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junha LEE ,  Seonkyoo LEE ,  Jeongdon IHM ,  Byunghoon JEONG

IPC: G11C16/06 ,  H01L23/66 ,  H01L25/065 ,  H01L25/18

Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.

公开(公告)号：US20210065753A1

公开(公告)日：2021-03-04

申请号：US17012845

申请日：2020-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junha LEE ,  Seonkyoo LEE ,  Jeongdon IHM ,  Byunghoon JEONG

IPC: G11C7/10 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.