公开(公告)号：US20240096382A1

公开(公告)日：2024-03-21

申请号：US18464618

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung KIM ,  Junghwan KWAK ,  Seungjun BAE ,  Chiweon YOON ,  Byungkwan CHUN ,  Youngmin JO

IPC: G11C7/10 ,  G06F13/16

CPC classification number: G11C7/1048 ,  G06F13/16 ,  G06F2213/16 ,  G11C2207/2254

Abstract: A ZQ calibration circuit includes: a ZQ controller configured to detect an end of one interface mode, among a plurality of interface modes in which ZQ calibration is supported, and to instruct a switch to another interface mode in response to the one interface mode coming to an end; a ZQ engine configured to generate a first reference voltage corresponding to the one interface mode through a multi-reference voltage generator, to generate a second reference voltage corresponding to the another interface mode in response to the switch to the another interface mode being instructed, to perform the ZQ calibration based on the first reference voltage or the second reference voltage, and to output a calibration code; and a ZQ driver configured to output an output signal through an input/output pad based on the calibration code.

公开(公告)号：US20190137563A1

公开(公告)日：2019-05-09

申请号：US16023736

申请日：2018-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Jung KWON ,  Seungjun BAE

IPC: G01R31/26 ,  G01R31/317 ,  G01R31/28 ,  H03K3/03

Abstract: A test circuit includes a first logic gate that receives a test signal or a first voltage, a second logic gate that receives the test signal, a third logic gate that receives an output of the first logic gate, an output of the second logic gate, or a second voltage, a fourth logic gate that receives the output of the first logic gate or the output of the second logic gate, and a power circuit that prevents the second and fourth logic gates from being driven by supplying power to the second and fourth logic gates when the first logic gate receives the first voltage and the third logic gate receives the second voltage.

公开(公告)号：US20240212729A1

公开(公告)日：2024-06-27

申请号：US18392199

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung KIM ,  Seonkyoo LEE ,  Seungjun BAE ,  Taesung LEE

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1066

Abstract: A storage device includes a first chip and a second chip configured to exchange data with the first chip. The first chip may transmit a data strobe signal and a plurality of data signals, applied with different delay times, to the second chip. The second chip may sample the plurality of data signals, applied with the different delay times, using the data strobe signal received from the first chip during data training.

公开(公告)号：US20180090186A1

公开(公告)日：2018-03-29

申请号：US15689260

申请日：2017-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Seok Kang ,  Seungjun BAE

IPC: G11C7/10 ,  H04L7/00 ,  G11C7/22 ,  H03L7/085 ,  H04L7/08 ,  H04L25/02

CPC classification number: G11C7/1072 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/085 ,  H03L7/091 ,  H04L7/0037 ,  H04L7/0337 ,  H04L7/08 ,  H04L7/10 ,  H04L25/0274 ,  H04L25/0288

Abstract: A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.