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公开(公告)号：US20240329886A1
公开(公告)日：2024-10-03
申请号：US18738172
申请日：2024-06-10
发明人： Daehoon NA , Jeongdon IHM , Jangwoo LEE , Byunghoon JEONG
CPC分类号： G06F3/0659 , G06F1/06 , G06F3/0611 , G06F3/0656 , G06F3/0679 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/0483
摘要： A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.
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公开(公告)号：US20210383848A1
公开(公告)日：2021-12-09
申请号：US17411421
申请日：2021-08-25
发明人： Byunghoon JEONG , Kyungtae KANG , Jangwoo LEE , Jeongdon IHM
IPC分类号： G11C7/22 , G11C7/10 , G11C8/18 , G11C29/42 , H03K19/173
摘要： A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
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公开(公告)号：US20230402076A1
公开(公告)日：2023-12-14
申请号：US18455904
申请日：2023-08-25
发明人： Byunghoon JEONG , Kyungtae KANG , Jangwoo LEE , Jeongdon IHM
IPC分类号： G11C7/22 , G11C7/10 , H03K19/173 , G11C8/18 , G11C29/42
CPC分类号： G11C7/222 , G11C7/1057 , G11C7/1063 , H03K19/1737 , G11C8/18 , G11C29/42 , G11C7/1084
摘要： A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
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公开(公告)号：US20210134336A1
公开(公告)日：2021-05-06
申请号：US17150307
申请日：2021-01-15
发明人： Daehoon NA , Jeongdon IHM , Jangwoo LEE , Byunghoon JEONG
摘要： A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.
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公开(公告)号：US20210065803A1
公开(公告)日：2021-03-04
申请号：US16834025
申请日：2020-03-30
发明人： Junha LEE , Seonkyoo LEE , Jeongdon IHM , Byunghoon JEONG
IPC分类号： G11C16/06 , H01L25/065 , H01L23/66 , H01L25/18
摘要： A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.
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公开(公告)号：US20220350541A1
公开(公告)日：2022-11-03
申请号：US17867008
申请日：2022-07-18
发明人： Daehoon NA , Jeongdon IHM , Jangwoo LEE , Byunghoon JEONG
摘要： A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.
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公开(公告)号：US20210104267A1
公开(公告)日：2021-04-08
申请号：US17001941
申请日：2020-08-25
发明人： Byunghoon JEONG , Kyungtae KANG , Jangwoo LEE , Jeongdon IHM
摘要： A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
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公开(公告)号：US20210103407A1
公开(公告)日：2021-04-08
申请号：US17031069
申请日：2020-09-24
发明人： Daehoon NA , Jeongdon IHM , Jangwoo LEE , Byunghoon JEONG
摘要： A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.
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公开(公告)号：US20210366546A1
公开(公告)日：2021-11-25
申请号：US17393784
申请日：2021-08-04
发明人： Junha LEE , Seonkyoo LEE , Jeongdon IHM , Byunghoon JEONG
IPC分类号： G11C16/06 , H01L23/66 , H01L25/065 , H01L25/18
摘要： A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.
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公开(公告)号：US20210226613A1
公开(公告)日：2021-07-22
申请号：US17222033
申请日：2021-04-05
发明人： Dongho SHIN , Kyungtae KANG , Junha LEE , Tongsung KIM , Jangwoo LEE , Jeongdon IHM , Byunghoon JEONG
摘要： A method of operating a system including a parameter monitoring circuit and a host, includes generating a first parameter applying a first code to a current parameter, wherein a first offset is applied to the first code; generating a first comparison result by comparing the first parameter with a reference parameter value; generating a second parameter applying a second code to the current parameter, wherein a second offset is applied to the second code; generating a second comparison result by comparing the second parameter with the reference parameter value; detecting an error in the current parameter, based on the first comparison result and the second comparison result; and providing a signal based on the error to the host.
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