公开(公告)号：US20230170891A1

公开(公告)日：2023-06-01

申请号：US18051138

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonju LEE ,  Jiyoung KIM ,  Jaehyun PARK ,  Seuk SON ,  Sooeun LEE ,  Dongchul CHOI

IPC: H03K5/26 ,  H03K3/037

CPC classification number: H03K5/26 ,  H03K3/037 ,  H03K2005/00286

Abstract: A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.

公开(公告)号：US20250062888A1

公开(公告)日：2025-02-20

申请号：US18934842

申请日：2024-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggeun KIM ,  Nakwon LEE ,  Jaehyun PARK ,  Kyeongjoon KO ,  Kangjik KIM ,  Seuk SON ,  Byunghyun LIM

IPC: H04L7/00

Abstract: A clock data recovery circuit includes an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal, a sampler circuit configured to sample input data based on the first clock pair and the second clock pair, and a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit, the I-Q merged phase interpolator circuit is configured to share analog inputs based on the control signal.

公开(公告)号：US20230114988A1

公开(公告)日：2023-04-13

申请号：US17957414

申请日：2022-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggeun KIM ,  Nakwon LEE ,  Jaehyun PARK ,  Kyeongjoon KO ,  Kangjik KIM ,  Seuk SON ,  Byunghyun LIM

IPC: H04L7/00

Abstract: A clock data recovery circuit includes an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal, a sampler circuit configured to sample input data based on the first clock pair and the second clock pair, and a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit, the I-Q merged phase interpolator circuit is configured to share analog inputs based on the control signal.

公开(公告)号：US20230099986A1

公开(公告)日：2023-03-30

申请号：US17943551

申请日：2022-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyun LEE ,  Hanseok KIM ,  Jiyoung KIM ,  Jaehyun PARK ,  Hyeonju LEE ,  Kangjik KIM ,  Sunggeun KIM ,  Seuk SON ,  Hobin SONG ,  Nakwon LEE

IPC: G01R25/04 ,  H03L7/08 ,  H03L7/085

Abstract: An apparatus for generating an output signal having a waveform that is repeated every period, includes a storage configured to store values corresponding to the waveform in a portion of a period of the output signal, a counter configured to generate a first index of a sample included in the output signal, a controller configured to generate at least one control signal based on the first index and the period of the output signal, and a calculation circuit configured to generate the output signal by calculating an output from the storage based on the at least one control signal.