公开(公告)号：US20180090493A1

公开(公告)日：2018-03-29

申请号：US15643062

申请日：2017-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Young Kwak ,  Ki Byung Park ,  Kyoung Hwan Yeo ,  Seung Jae Lee ,  Kyung Yub Jeon ,  Seung Seok Ha ,  Sang Jin Hyun

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate. The semiconductor device includes first and second source/drain regions in the semiconductor substrate. Moreover, the semiconductor device includes a multi-layer device isolation region in the semiconductor substrate between the first and second source/drain regions. The multi-layer device isolation region includes a protruding portion that protrudes away from the semiconductor substrate beyond respective uppermost surfaces of the first and second source/drain regions.

公开(公告)号：US10937887B2

公开(公告)日：2021-03-02

申请号：US16425337

申请日：2019-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guk Il An ,  Keun Hwi Cho ,  Dae Won Ha ,  Seung Seok Ha

IPC: H01L29/51 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78 ,  H01L49/02

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

公开(公告)号：US12107139B2

公开(公告)日：2024-10-01

申请号：US18369450

申请日：2023-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guk Il An ,  Keun Hwi Cho ,  Dae Won Ha ,  Seung Seok Ha

IPC: H01L29/51 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78 ,  H01L49/02

CPC classification number: H01L29/516 ,  H01L23/5226 ,  H01L27/0886 ,  H01L28/40 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

公开(公告)号：US10566326B2

公开(公告)日：2020-02-18

申请号：US15643062

申请日：2017-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Young Kwak ,  Ki Byung Park ,  Kyoung Hwan Yeo ,  Seung Jae Lee ,  Kyung Yub Jeon ,  Seung Seok Ha ,  Sang Jin Hyun

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate. The semiconductor device includes first and second source/drain regions in the semiconductor substrate. Moreover, the semiconductor device includes a multi-layer device isolation region in the semiconductor substrate between the first and second source/drain regions. The multi-layer device isolation region includes a protruding portion that protrudes away from the semiconductor substrate beyond respective uppermost surfaces of the first and second source/drain regions.

公开(公告)号：US09741854B2

公开(公告)日：2017-08-22

申请号：US14959457

申请日：2015-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hee Bai ,  Kyoung Hwan Yeo ,  Seung Seok Ha ,  Seung Ju Park ,  Do Hyoung Kim ,  Myeong Cheol Kim ,  Jae Hyoung Koo ,  Ki Byung Park

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7851

Abstract: There is provided a method for manufacturing a semiconductor device including a substrate including a plurality of active regions, a plurality of gate electrodes extending in a first direction to intersect a portion of the plurality of active regions, and including first and second gate electrodes disposed to be adjacent to each other in the first direction, a gate isolation portion disposed between the first and second gate electrodes. The gate isolation portion includes a first layer and second layers disposed on both ends of the first layer in a second direction perpendicular to the first direction.

公开(公告)号：US11929367B2

公开(公告)日：2024-03-12

申请号：US17977031

申请日：2022-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Seok Ha ,  Hyun Seung Song ,  Hyo Jin Kim ,  Kyoung Mi Park ,  Guk Il An

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

公开(公告)号：US11799013B2

公开(公告)日：2023-10-24

申请号：US17838573

申请日：2022-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guk Il An ,  Keun Hwi Cho ,  Dae Won Ha ,  Seung Seok Ha

IPC: H01L29/51 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78 ,  H01L49/02

CPC classification number: H01L29/516 ,  H01L23/5226 ,  H01L27/0886 ,  H01L28/40 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

公开(公告)号：US11488953B2

公开(公告)日：2022-11-01

申请号：US17036355

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Seok Ha ,  Hyun Seung Song ,  Hyo Jin Kim ,  Kyoung Mi Park ,  Guk Il An

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/66 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

公开(公告)号：US10825809B2

公开(公告)日：2020-11-03

申请号：US16290199

申请日：2019-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Seok Ha ,  Hyun Seung Song ,  Hyo Jin Kim ,  Kyoung Mi Park ,  Guk Il An

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/66 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

公开(公告)号：US12238941B2

公开(公告)日：2025-02-25

申请号：US18436812

申请日：2024-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Seok Ha ,  Hyun Seung Song ,  Hyo Jin Kim ,  Kyoung Mi Park ,  Guk Il An

IPC: H10D84/83 ,  H01L21/308 ,  H10D30/01 ,  H10D30/62 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.