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    Semiconductor devices and methods for fabricating the same
    1.
    发明授权
    Semiconductor devices and methods for fabricating the same 有权

    公开(公告)号：US12261204B2

    公开(公告)日：2025-03-25

    申请号：US18615049

    申请日：2024-03-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mun Hyeon Kim ,  Kern Rim ,  Dae Won Ha

    IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first horizontal direction on the substrate, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, a source/drain region on at least one side of the gate electrode, a source/drain contact extending into the source/drain region and including a filling layer and a barrier layer along a sidewall of the filling layer, and a silicide layer between the source/drain region and the filling layer, the silicide layer including a first sidewall in contact with the filling layer and a second sidewall in contact with the source/drain region, wherein the barrier layer is not between the filling layer and the source/drain region.

    Semiconductor device and method of fabricating the same
    3.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US11139271B2

    公开(公告)日：2021-10-05

    申请号：US16508857

    申请日：2019-07-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung Min Kim ,  Dae Won Ha

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

    Abstract: A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.

    SEMICONDUCTOR DEVICES INCLUDING A STRESS PATTERN
    4.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING A STRESS PATTERN 审中-公开

    公开(公告)号：US20200083377A1

    公开(公告)日：2020-03-12

    申请号：US16402292

    申请日：2019-05-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung Min Kim ,  Hyo Jin Kim ,  Dae Won Ha

    IPC: H01L29/78 ,  H01L21/762

    Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure including a stress structure and a semiconductor region that are sequentially stacked on a substrate. The semiconductor device includes a field insulation layer on a portion of the fin structure. The semiconductor device includes a gate electrode on the fin structure. Moreover, the stress structure includes an oxide.

    Semiconductor device including contact structure
    5.
    发明授权
    Semiconductor device including contact structure 有权

    公开(公告)号：US10153212B2

    公开(公告)日：2018-12-11

    申请号：US15449302

    申请日：2017-03-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hwi Chan Jun ,  Chang Hwa Kim ,  Dae Won Ha

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/522

    Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

    SEMICONDUCTOR MEMORY DEVICES
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20240422987A1

    公开(公告)日：2024-12-19

    申请号：US18398336

    申请日：2023-12-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung Hwan Lee ,  Myung Hun Woo ,  Dae Won Ha

    IPC: H10B51/30 ,  H10B51/40

    Abstract: There is provided a semiconductor memory device comprising: a first word line; a second word line spaced apart from the first word line, a back gate electrode between the first word line and the second word line; a first channel pattern between the first word line and the back gate electrode; a second channel pattern between the second word line and the back gate electrode; a first gate insulating film between the first word line and the first channel pattern; a second gate insulating film between the second word line and the second channel pattern; a first bit line on the first channel pattern and the second channel pattern, wherein the first bit line is connected to the first channel pattern; and a second bit line on the first channel pattern and the second channel pattern, wherein the second bit line is connected to the second channel pattern.

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