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公开(公告)号：US09098381B2
公开(公告)日：2015-08-04
申请号：US13734520
申请日：2013-01-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyoungmoon Ahn , Jonghoon Shin , Yong Ki Lee , Ji-Su Kang , Sun-Soo Shin
IPC: G06F7/72
Abstract: A modular arithmetic unit includes a first input generator receiving first data to generate a first operand; a second input generator receiving second data to generate a second operand; an accumulator performing an accumulate/shift operation to add the first and second operands and outputting the carry and sum; a carry propagation adder adding the carry and the sum to output a result; and a data handler receiving either external data or the result and outputting the first data and the second data.
Abstract translation: 模块运算单元包括接收第一数据以产生第一操作数的第一输入发生器; 接收第二数据以产生第二操作数的第二输入发生器; 累加器执行累加/移位操作以添加第一和第二操作数并输出进位和和; 一个进位传播加法器，加上进位和和输出一个结果; 以及接收外部数据或结果并输出第一数据和第二数据的数据处理器。
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公开(公告)号：US09448768B2
公开(公告)日：2016-09-20
申请号：US13792642
申请日：2013-03-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong Ki Lee , Jonghoon Shin , KyoungMoon Ahn , Ji-Su Kang , Sun-Soo Shin
IPC: G06F7/72
Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.
Abstract translation: 提供了一种模数乘法器和一种模乘法。 模数乘法器包括：第一寄存器，其存储在先前周期计算的先前累积值; 存储在前一周期计算的先前商的第二寄存器; 商产生器，其使用从所述第一寄存器输出的存储的先前累积值生成商; 以及累加器，其接收操作数，乘数的位值，存储的先前累积值和存储的先前商，以计算当前周期中的累积值，其中计算的累加值被更新为第一寄存器，并且 生成商被更新到第二个寄存器。
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3.发明授权公开(公告)号：US09164732B2
公开(公告)日：2015-10-20
申请号：US14139113
申请日：2013-12-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong Ki Lee , Sun-Soo Shin , Jonghoon Shin , Kyoung Moon Ahn , Ji-Su Kang , Kee Moon Chun
CPC classification number: G06F7/722 , G06F7/728 , H04L9/3013 , H04L9/302
Abstract: A multiplication method and a modular multiplier are provided. The multiplication method includes transforming a redundant-form multiplier by adding a recoding constant to the multiplier, performing recoding by using the transformed multiplier, and performing partial multiplication between the multiplier and a multiplicand using result values of the recoding.
Abstract translation: 提供乘法和模乘法。 乘法方法包括：通过向乘法器添加重新编码常数来变换冗余形式乘法器，通过使用变换乘数执行重新编码，并且使用重新编码的结果值，在乘法器和乘法器之间执行部分乘法。
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Patent Agency Ranking
公开(公告)号：US09841950B2
公开(公告)日：2017-12-12
申请号：US15242768
申请日：2016-08-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong Ki Lee , Jonghoon Shin , KyoungMoon Ahn , Ji-Su Kang , Sun-Soo Shin
IPC: G06F7/72
Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.
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公开(公告)号：US09811318B2
公开(公告)日：2017-11-07
申请号：US14672656
申请日：2015-03-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jonghoon Shin , Sun-Soo Shin , Kyoungmoon Ahn , Yong Ki Lee
CPC classification number: G06F7/728 , G06F7/5338
Abstract: A Montgomery multiplier includes a partial product computing unit for multiplying a multiplicand and a multiplier; a modulus reduction computing unit for performing a multiplication of a modulus and a quotient that reflects a quotient sign; an accumulation unit for accumulating in a intermediate value an output value of the partial product computing unit and an output value of the modulus reduction computing unit from a previous cycle; a quotient computing unit for receiving an accumulation value of the accumulation unit during a current cycle and calculating a quotient sign to be used during a next cycle; and a quotient sign determination unit for determining a quotient sign to be used during a next cycle from the multiplicand, the multiplier and the quotient.
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6.发明申请公开(公告)号：US20130262544A1
公开(公告)日：2013-10-03
申请号：US13716994
申请日：2012-12-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Ki Lee , Jong-Hoon Shin , Kyoung-Moon Ahn , Ji-Su Kang , Sun-Soo Shin
CPC classification number: G06F7/533 , G06F7/5324 , G06F7/5338 , G06F7/588 , G06F2207/7257
Abstract: An electronic multiplier, such as a multiplication circuit, may include a partial product generator, a Booth code encoder and an accumulator. The partial product generator may generate partial product data based on a Booth code and multiplicand data. The Booth code encoder may generate the Booth code based on multiplier data. The Booth code may include a zero-generation Booth code and a zero-avoidance Booth code. The Booth code encoder may selectively generate the zero-generation Booth code or the zero-avoidance Booth code when the partial product data correspond to a partial product of zero. The accumulator accumulates the partial product data to provide a multiplication result of the multiplicand data and the multiplier data.
Abstract translation: 诸如乘法电路的电子倍增器可以包括部分乘积发生器，布斯码编码器和累加器。 部分积发生器可以基于布斯码和被乘数数据生成部分乘积数据。 布斯码编码器可以基于乘数数据生成布斯码。 展位代码可以包括零代布斯代码和零回避布斯码。 当部分乘积数据对应于零的部分乘积时，布斯克编码器可以选择性地生成零代布斯码或零回避布斯码。 累加器积累部分乘积数据以提供被乘数数据和乘数数据的相乘结果。
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公开(公告)号：US09633185B2
公开(公告)日：2017-04-25
申请号：US14556397
申请日：2014-12-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jonghoon Shin , KyoungMoon Ahn , Mijung Noh , Yong Ki Lee , Sun-Soo Shin
IPC: G06F21/00 , G06F21/31 , G06F21/60 , G01R31/3185
CPC classification number: G06F21/31 , G01R31/318588 , G06F21/602
Abstract: A method of debugging a device which includes a plurality of processors is provided. The method includes verifying a request to initiate authentication that is provided to the device to a user; performing a challenge-response authentication operation between the user and the device in response to the request to initiate authentication being a request from a non-malicious user; activating or deactivating an access to a Joint Test Action Group (JTAG) port of each of the processors, based on access control information from the user; and permitting a debugging operation via an access that is activated.
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8.发明申请Arithmetic Devices, Montgomery Parameter Calculation Method and Modular Multiplication Method Thereof 审中-公开算术设备，蒙哥马利参数计算方法和模块化乘法方法公开(公告)号：US20160034255A1
公开(公告)日：2016-02-04
申请号：US14722761
申请日：2015-05-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-Soo Shin , Jonghoon Shin , KyoungMoon Ahn , Yong Ki Lee
IPC: G06F7/523
CPC classification number: G06F7/728
Abstract: Disclosed are arithmetic devices, a method of a Montgomery parameter calculation thereof and a Montgomery multiplication method thereof. The method of the Montgomery parameter calculation of the arithmetic devices includes detecting a position of a most significant bit (MSB) of a modulus, calculating an initial value using position information about the detected MSB, and calculating an intermediate value and a Montgomery parameter by repeatedly performing a Montgomery addition or a Montgomery multiplication with respect to the initial value.
Abstract translation: 公开了算术装置，其计算Montgomery参数的方法和Montgomery乘法方法。 算术装置的蒙哥马利参数计算方法包括检测模数的最高有效位（MSB）的位置，使用关于检测到的MSB的位置信息计算初始值，并通过重复地计算中间值和蒙哥马利参数 执行Montgomery加法或Montgomery乘法相对于初始值。
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