公开(公告)号：US10573652B2

公开(公告)日：2020-02-25

申请号：US15945401

申请日：2018-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-Dong Lee ,  Jun-Won Lee ,  Ki Seok Lee ,  Bong-Soo Kim ,  Seok Han Park ,  Sung Hee Han ,  Yoo Sang Hwang

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.

公开(公告)号：US10319726B2

公开(公告)日：2019-06-11

申请号：US15642394

申请日：2017-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Cheol Nam ,  Sung Hee Han ,  Dae Sun Kim

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L21/765 ,  H01L27/108

Abstract: A semiconductor device includes a substrate including an active region and an element isolation region defining the active region, a gate trench extending into the element isolation region and penetrating the active region, and a gate structure filling the gate trench and including a first conductivity-type semiconductor layer, a conductive layer, and a second conductivity-type semiconductor layer, sequentially stacked from a lower portion of the gate trench.

公开(公告)号：US11696436B2

公开(公告)日：2023-07-04

申请号：US17035082

申请日：2020-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Seok Lee ,  Jae Hyun Yoon ,  Kyu Jin Kim ,  Keun Nam Kim ,  Hui-Jung Kim ,  Kyu Hyun Lee ,  Sang-Il Han ,  Sung Hee Han ,  Yoo Sang Hwang

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053

Abstract: A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part.

公开(公告)号：US11594538B2

公开(公告)日：2023-02-28

申请号：US17469340

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Ho Lee ,  Eun A Kim ,  Ki Seok Lee ,  Jay-Bok Choi ,  Keun Nam Kim ,  Yong Seok Ahn ,  Jin-Hwan Chun ,  Sang Yeon Han ,  Sung Hee Han ,  Seung Uk Han ,  Yoo Sang Hwang

IPC: H01L21/00 ,  H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

公开(公告)号：US20190214293A1

公开(公告)日：2019-07-11

申请号：US16028794

申请日：2018-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu Jin Kim ,  Min Su Choi ,  Sung Hee Han ,  Bong Soo Kim ,  Yoo Sang Hwang

IPC: H01L21/762 ,  H01L27/108

CPC classification number: H01L21/76229 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a cell region and a peripheral region having different active region densities, forming cell trenches for limiting cell active regions in the cell region so that the cell active regions are formed to be spaced apart by a first width in a first direction and by a second width in a second direction, forming peripheral trenches for limiting a peripheral active region in the peripheral region, and forming, in the cell trenches, a first insulating layer continuously extending in the first and second directions and contacting sidewalls of the cell active regions, and having a thickness equal to or greater than half of the first width and less than half of the second width.

公开(公告)号：US11121134B2

公开(公告)日：2021-09-14

申请号：US16860276

申请日：2020-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Ho Lee ,  Eun A Kim ,  Ki Seok Lee ,  Jay-Bok Choi ,  Keun Nam Kim ,  Yong Seok Ahn ,  Jin-Hwan Chun ,  Sang Yeon Han ,  Sung Hee Han ,  Seung Uk Han ,  Yoo Sang Hwang

IPC: H01L21/00 ,  H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.