公开(公告)号：US20180357166A1

公开(公告)日：2018-12-13

申请号：US15781316

申请日：2016-12-02

申请人： Samsung Electronics Co., Ltd.

发明人： Changhun YU ,  Wonjin KIM ,  Hyunsik KIM ,  Sunho MOON ,  Minwook AHN ,  Rakie KIM ,  Kyoungsoo CHO ,  Nikunj SAUNSHI ,  Parichay KAPOOR ,  Pankaj AGARWAL ,  Won-Sub KIM ,  Jin-Hyo KIM ,  Hyunghoon KIM ,  Jisu OH ,  Keongho LEE ,  Seung-Beom LEE ,  Jinseok LEE ,  Dong-Gi JANG ,  Subin JO ,  Apoorv KANSAL

IPC分类号： G06F12/06 ,  G06F12/0882 ,  G06F12/0817 ,  G06F12/1009

CPC分类号： G06F12/0646 ,  G06F12/0822 ,  G06F12/0882 ,  G06F12/1009

摘要： The present disclosure relates to system resource management in a variety of situations. The present disclosure provides a method and an apparatus for reducing memory requirements and improving processing speed when an electronic device performs padding for a particular arithmetic operation on data. To achieve the above objective, a method for operating an electronic device according to the present disclosure comprises the steps of: reading a first portion of data from a first memory; determining a first padding address based on the address of a byte belonging to a boundary region of the data among a plurality of bytes included in the first portion; writing values of the plurality of bytes and a value corresponding to the first padding address to a second memory; and reading a second portion of the data from the first memory.

公开(公告)号：US20140317628A1

公开(公告)日：2014-10-23

申请号：US14258795

申请日：2014-04-22

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Won-Sub KIM

IPC分类号： G06F9/48 ,  G06F3/06

CPC分类号： G06F3/0671 ,  G06F8/4452

摘要： Provided are a scheduling apparatus and method for effective processing support of long routing in a coarse grain reconfigurable array (CGRA)-based processor. The scheduling apparatus includes: an analyzer configured to analyze a degree of skew in a data flow of a program; a determiner configured to determine whether operations in the data flow utilize a memory spill based on the analyzed degree of skew; and an instruction generator configured to eliminate dependency between the operations that are determined to utilize the memory spill, and to generate a memory spill instruction.

摘要翻译： 提供了一种用于在基于粗粒度可重配置阵列（CGRA）的处理器中有效处理长路由选择的调度装置和方法。 调度装置包括：分析器，被配置为分析程序的数据流中的偏斜度; 确定器，被配置为基于分析的偏斜度来确定数据流中的操作是否利用存储器溢出; 以及指令生成器，其被配置为消除确定为利用所述存储器溢出的操作之间的依赖性，并且生成存储器溢出指令。

公开(公告)号：US20170068620A1

公开(公告)日：2017-03-09

申请号：US15121999

申请日：2015-02-26

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Won-Sub KIM ,  Tai-song JIN ,  Do-hyung KIM ,  Seung-won LEE

IPC分类号： G06F12/0844 ,  G06F9/48 ,  G06F13/16 ,  G06F9/52

CPC分类号： G06F12/0844 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/4831 ,  G06F9/52 ,  G06F13/161 ,  G06F13/1642 ,  G06F13/372 ,  G06F13/376 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/281 ,  G06F2212/608

摘要： A method of preventing a bank conflict in a memory includes determining processing timing of each of threads of function units to access a first memory bank in which occurrence of a bank conflict is expected, setting a variable latency of each of the threads for sequential access of the threads according to the determined processing timing, sequentially storing the threads in a data memory queue according to the determined processing timing, and performing an operation by allowing the threads stored in the data memory queue to sequentially access the first memory bank whenever the variable latency of each of the threads passes.

摘要翻译： 一种防止存储器中的存储体冲突的方法包括：确定功能单元的每个线程的处理定时，以访问预期发生存储体冲突的第一存储体，设置每个线程的可变等待时间以顺序访问 根据所确定的处理定时，线程根据所确定的处理定时顺序地将线程存储在数据存储器队列中，并且通过允许存储在数据存储器队列中的线程在可变延迟时间内顺序地存取第一存储体，执行操作 的每个线程通过。

公开(公告)号：US20140259020A1

公开(公告)日：2014-09-11

申请号：US14197591

申请日：2014-03-05

申请人： Samsung Electronics Co., Ltd.

发明人： Won-Sub KIM ,  Yoonseo CHOI ,  Hae-Woo PARK

IPC分类号： G06F9/48

CPC分类号： G06F15/7885 ,  G06F9/4881

摘要： A scheduler and scheduling method perform scheduling for a reconfigurable architecture. The scheduling, performed by the scheduler, includes path information extracting including extracting direct path information and indirect path information between functional units in a reconfigurable array complying with predefined architecture requirements, based on architecture information of the reconfigurable array, command selecting including selecting a command from a data flow graph (DFG) showing commands to be executed by the reconfigurable array, and scheduling including scheduling the selected command based on the extracted direct path information and indirect path information.

摘要翻译： 调度器和调度方法对可重构架构执行调度。 由调度器执行的调度包括路径信息提取，包括基于可重配置阵列的体系结构信息，在可重配置阵列的可重构阵列中的功能单元之间提取直接路径信息和间接路径信息，命令选择包括从 显示由可重配置阵列执行的命令的数据流图（DFG），以及包括基于所提取的直接路径信息和间接路径信息来调度所选择的命令的调度。