公开(公告)号：US20170103999A1

公开(公告)日：2017-04-13

申请号：US15291521

申请日：2016-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Hoon LEE ,  Keejeong RHO ,  Sejun PARK ,  Jinhyun SHIN ,  Dong-Sik LEE ,  Woong-Seop LEE

IPC: H01L27/115 ,  H01L23/528

CPC classification number: H01L27/11582 ,  G11C16/08 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/1157

Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.