公开(公告)号：US20150380421A1

公开(公告)日：2015-12-31

申请号：US14848423

申请日：2015-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang SIM ,  Jinhyun SHIN ,  Jong-Min LEE

IPC: H01L27/115 ,  H01L21/764

CPC classification number: H01L27/11524 ,  H01L21/764 ,  H01L29/42324

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

Abstract translation: 提供一种半导体存储器件及其制造方法。 半导体存储器件可以包括半导体衬底，其具有限定第一区域中的有源区域的第一沟槽和设置在第一区域周围的第二区域中的第二沟槽，设置在第一区域上的栅电极以跨越有源区域， 存储图案，设置在所述栅电极和所述有源区之间，阻挡绝缘层，设置在所述栅电极和所述电荷存储图案之间并在所述第一沟槽上延伸以限定所述第一沟槽中的第一气隙，以及间隔开的绝缘图案 从第二沟槽的底表面到第二沟槽中限定第二气隙。

公开(公告)号：US20170103999A1

公开(公告)日：2017-04-13

申请号：US15291521

申请日：2016-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Hoon LEE ,  Keejeong RHO ,  Sejun PARK ,  Jinhyun SHIN ,  Dong-Sik LEE ,  Woong-Seop LEE

IPC: H01L27/115 ,  H01L23/528

CPC classification number: H01L27/11582 ,  G11C16/08 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/1157

Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.