公开(公告)号：US20230057630A1

公开(公告)日：2023-02-23

申请号：US17870200

申请日：2022-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongyeon WOO ,  Minje KIM ,  Woongseop LEE ,  Dongjun YU ,  Jinsoo LIM

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: A device includes: a stack structure including first and second stack regions; first and second separation structures penetrating the stack structure; and vertical structures penetrating the stack structure, including first and second vertical memory structures spaced from the first separation structure by different lengths. The first and second vertical memory structures each include a lower portion, penetrating the first stack region, and an upper portion penetrating the second stack region. A first distance between a center of an upper region of the upper portion of the first vertical memory structure and a center of an upper region of the upper portion of the second vertical memory structure is different from a second distance between a center of an upper region of the lower portion of the first vertical memory structure and a center of an upper region of the lower portion of the second vertical memory structure.

公开(公告)号：US20240365543A1

公开(公告)日：2024-10-31

申请号：US18435328

申请日：2024-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taegon LEE ,  Minkyu KANG ,  Sungjun KIM ,  Woongseop LEE ,  Eunsuk CHO ,  Jongyoon CHOI ,  Hyungyu HWANG

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H10B80/00

Abstract: A semiconductor device comprising; a first semiconductor structure including a substrate, circuit elements on the substrate, and circuit interconnection lines on the circuit elements; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes, a plate layer, a plurality of gate electrodes spaced apart from each other and stacked on the plate layer in a first direction, perpendicular to an upper surface of the plate layer, the gate electrodes including a lower select gate electrode, memory gate electrodes, and an upper select gate electrode sequentially stacked, channel structures passing through the lower select gate electrode and the memory gate electrodes and extending in the first direction, stud structures passing through the upper select gate electrode and respectively connected to the channel structures.