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公开(公告)号:US20240222267A1
公开(公告)日:2024-07-04
申请号:US18396813
申请日:2023-12-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Byoungil LEE , Seungbeom KO , Jongyoon CHOI
IPC: H01L23/522 , G11C16/04 , H01L23/528 , H01L25/065 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00
CPC classification number: H01L23/5226 , G11C16/0483 , H01L23/5283 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00 , H01L2225/06506
Abstract: A semiconductor device comprising: a stack structure on a substrate including gate electrodes and insulating layers alternately stacked; a first through via extending through the stack structure; and a second through via spaced apart from the first through via, wherein the second through via extends through the stack structure, wherein the second through via is electrically connected to a first gate electrode that is farthest one among the gate electrodes from the substrate in the vertical direction, wherein a gate pad is on and contacts the first gate electrode, and the first through via includes: a vertical pattern; first and second protrusions that protrude from the vertical pattern, wherein the first protrusion overlaps a portion of the first gate electrode in the horizontal direction; and the second protrusion overlaps a second gate electrode in the horizontal direction, wherein the second gate electrode is spaced apart from the second through via.
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公开(公告)号:US20240365543A1
公开(公告)日:2024-10-31
申请号:US18435328
申请日:2024-02-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Taegon LEE , Minkyu KANG , Sungjun KIM , Woongseop LEE , Eunsuk CHO , Jongyoon CHOI , Hyungyu HWANG
CPC classification number: H10B43/27 , H10B41/10 , H10B41/27 , H10B43/10 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73215 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H10B80/00
Abstract: A semiconductor device comprising; a first semiconductor structure including a substrate, circuit elements on the substrate, and circuit interconnection lines on the circuit elements; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes, a plate layer, a plurality of gate electrodes spaced apart from each other and stacked on the plate layer in a first direction, perpendicular to an upper surface of the plate layer, the gate electrodes including a lower select gate electrode, memory gate electrodes, and an upper select gate electrode sequentially stacked, channel structures passing through the lower select gate electrode and the memory gate electrodes and extending in the first direction, stud structures passing through the upper select gate electrode and respectively connected to the channel structures.
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