公开(公告)号：US20230057630A1

公开(公告)日：2023-02-23

申请号：US17870200

申请日：2022-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongyeon WOO ,  Minje KIM ,  Woongseop LEE ,  Dongjun YU ,  Jinsoo LIM

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: A device includes: a stack structure including first and second stack regions; first and second separation structures penetrating the stack structure; and vertical structures penetrating the stack structure, including first and second vertical memory structures spaced from the first separation structure by different lengths. The first and second vertical memory structures each include a lower portion, penetrating the first stack region, and an upper portion penetrating the second stack region. A first distance between a center of an upper region of the upper portion of the first vertical memory structure and a center of an upper region of the upper portion of the second vertical memory structure is different from a second distance between a center of an upper region of the lower portion of the first vertical memory structure and a center of an upper region of the lower portion of the second vertical memory structure.

公开(公告)号：US20220343147A1

公开(公告)日：2022-10-27

申请号：US17408951

申请日：2021-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soon-Wan KWON ,  Minje KIM ,  Sang Joon KIM

IPC: G06N3/063 ,  G06N3/04 ,  G06F7/501 ,  G06F17/16 ,  H03M1/12

Abstract: A neural network apparatus includes: a first processing circuit and a second processing circuit each configured to perform a vector-by-matrix multiplication (VMM) operation on a weight and an input activation; a first register configured to store an output of the first processing circuit; an adder configured to add an output of the first register and an output of the second processing circuit; a second register configured to store an output of the adder; and an input circuit configured to input a same input activation to the first processing circuit and the second processing circuit and control the first processing circuit and the second processing circuit.

公开(公告)号：US20250068938A1

公开(公告)日：2025-02-27

申请号：US18426830

申请日：2024-01-30

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Minje KIM ,  Jaejin LEE ,  Dohun KIM ,  Jinpyo KIM ,  Soon-Wan KWON ,  Heehoon KIM ,  Daeyoung PARK

IPC: G06N5/022 ,  G06F1/3203 ,  G06N3/04

Abstract: A processor-implemented method includes obtaining a benchmark execution result, receiving input data comprising a neural network model subject to prediction and analysis requirement information, receiving information on hardware of a device in which the neural network model is run, building a prediction model based on the benchmark execution result and the hardware information, extracting layer information respectively corresponding to a plurality of layers configuring the neural network model, and predicting either one or both of operation performance information and energy efficiency information respectively corresponding to the plurality of layers by inputting the analysis requirement information and the layer information to the prediction model.

公开(公告)号：US20240249110A1

公开(公告)日：2024-07-25

申请号：US18344201

申请日：2023-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minje KIM ,  Soon-Wan KWON ,  Wooseok YI ,  Jangho AN

IPC: G06N3/04

CPC classification number: G06N3/04

Abstract: A device includes: an operation module configured to store and operate a weight for an operation of a layer of a neural network model; a control module configured to generate setting information for performing the operation of the layer by the neural network model using the stored weight; an input module configured to receive input data for the operation of the layer based on the generated setting information; a merging module configured to receive operation results of the operation of the layer from the operation module and merge the received operation results of the layer; a post-processing module configured to receive the merged operation results of the layer from the merging module and post-process the received merged operation results of the layer; and an output stream module configured to convert and store the post-processed operation results based on the generated setting information.